LDPC Bit Interleaver Permutation for Burst Error Distribution

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Solution Overview

Problem

Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.

Innovation Solution

A bit interleaver optimized for an LDPC coder with a length of 16200 and code rate of 4/15, using 256-symbol mapping, is designed to effectively distribute burst errors by interleaving LDPC codewords on a bit group basis with a specific permutation order, suitable for next-generation broadcasting systems like ATSC 3.0.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation

Engineering Contradiction:

Improvesystem performanceVSAvoidinterleaver design complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the LDPC codeword into multiple bit groups (e.g., 45 bit groups of 360 bits each) and applies separate permutation operations to each group. This segmentation allows the interleaver to effectively distribute burst errors across different groups while maintaining a manageable design complexity through standardized group processing

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic permutation sequences that adapt to different modulation orders and code rates. The interleaver uses variable permutation patterns (e.g., different sequences for 256-QAM vs. other modulations) to optimize performance for specific channel conditions and system configurations

Inventive Principle:

Principle #15Dynamics

2Reliability

If the bit interleaver is optimized for specific modulation order and code rate parameters, then performance improves, but the adaptability to different broadcasting standards decreases

Engineering Contradiction:

Improveerror correction performanceVSAvoidcompatibility with broadcasting standards

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent systematically varies key parameters including modulation order (e.g., 256-QAM), code rate (e.g., 4/15), block length (e.g., 16200 bits), and bit group size (e.g., 360 bits) to optimize performance for specific broadcasting applications. The design allows parameter adjustment while maintaining the core interleaving structure

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent creates a universal interleaver framework that can serve multiple broadcasting standards (DVB-T2, DVB-NGH, ATSC 3.0) by configuring parameters according to each standard's requirements. The same basic architecture handles different modulation schemes, code rates, and block lengths through parameterization rather than requiring separate designs

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10784894B2Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same

Publication Date: 2020.09.22 ELECTRONICS & TELECOMM RES INST

AI summary

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.