LDPC Bit Interleaver Layout for 4096-Symbol Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 2/15, employing 4096-symbol mapping, which interleaves the LDPC codeword on a bit group basis using a specific permutation order to effectively distribute burst errors, suitable for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent segments the LDPC codeword into multiple bit groups (e.g., 180 bit groups of 360 bits each) and applies independent interleaving operations to each group using different permutation orders. This segmentation allows the system to distribute burst errors across multiple groups while maintaining a structured approach that balances performance improvement with implementation complexity
Solution Approach 2:
The patent applies different interleaving strategies to different parts of the codeword. Specifically, it uses different permutation orders for different bit groups, and applies distinct interleaving methods to information bits versus parity bits. This local differentiation optimizes error distribution for specific channel conditions while maintaining overall system performance
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then performance improves, but the system loses flexibility in selecting different modulation and coding schemes
Solution Approach 1:
The patent implements a dynamic interleaver configuration where the permutation order and bit group parameters are adjusted based on the selected modulation order and LDPC code rate. The system can adaptively select from multiple predefined permutation orders (e.g., different sequences for different code rates) and adjust bit group sizes dynamically, allowing optimization for specific operating conditions while maintaining flexibility to switch between different BICM configurations
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.