LDPC Bit Interleaver Placement for Lower Decoder Complexity
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Solution Overview
Problem
The location of an interleaver with Low-Density Parity-Check (LDPC) code in 5G New Radio (NR) mobile communications is not defined, leading to varying decoder complexities based on code rates, which affects the efficiency of data decoding.
Innovation Solution
Proposing two schemes for the location of a bit-level interleaver relative to a circular buffer: one where the interleaver is before the buffer, resulting in lower code rates and higher decoder complexity, and another where the interleaver is after the buffer, achieving a suitable code rate for lower decoder complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interleaver is placed before the circular buffer, then the code rate is reduced, but the decoder complexity increases
Solution Approach 1:
The interleaver is placed before the circular buffer to perform preliminary scrambling of the encoded bits before rate matching. This preliminary action ensures that even though the code rate is reduced, the decoder complexity is managed by performing the interleaving operation earlier in the encoding chain, where it can be more efficiently implemented.
2Device complexity
If the interleaver is placed after the circular buffer, then the decoder complexity is reduced, but the code rate increases
Solution Approach 1:
The interleaver is positioned after the circular buffer to perform the interleaving operation after rate matching has been completed. This timing allows the decoder to work with a higher code rate while maintaining lower complexity, as the interleaving is performed at a stage where it does not add significant computational burden to the decoding process.
Data Source
AI summary
Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.