LDPC Bit Interleaver Layout for QPSK Burst Error Resilience
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code length and rate.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and a code rate of 7/15, combined with a QPSK modulator, effectively distributes burst errors by interleaving on a bit group basis using a specific permutation order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bit-by-bit interleaver is used in BICM systems, then the system can provide bandwidth-efficient transmission and flexibility in modulation order and code parameters, but the system suffers from rapid performance degradation due to burst errors in digital broadcast channels
Solution Approach 1:
The interleaver divides the codeword into multiple bit groups (e.g., 180 bit groups of 360 bits each) and performs interleaving at the bit group level rather than individual bit level. This segmentation allows the system to maintain bandwidth efficiency while providing sufficient dispersion of burst errors across different bit groups, thereby resolving the contradiction between bandwidth efficiency and reliability.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then the system achieves excellent performance, but the device complexity increases due to the need for optimized design
Solution Approach 1:
The interleaver uses parameterized design where the bit group size and number of bit groups can be adjusted based on the parallel factor of the LDPC codeword. By changing these parameters according to specific modulation orders and code rates (e.g., QPSK with 64800-length LDPC code), the system achieves optimized performance for different configurations without requiring completely different interleaver structures, thus managing design complexity while maintaining high performance.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.