LDPC Bit Interleaving for 1024-Symbol Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 3/15, using 1024-symbol mapping, which interleaves the LDPC codeword on a bit group basis with a parallel factor of 360, effectively distributing burst errors through a specific permutation order, suitable for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent divides the LDPC codeword into multiple bit groups (e.g., 180 bit groups for a 64800-length codeword with parallel factor 360) and applies independent permutation operations to each group. This segmentation allows the interleaver to effectively distribute burst errors across different groups while maintaining a manageable computational structure for each individual group.
Solution Approach 2:
The patent optimizes the permutation order parameters specifically for the given LDPC code parameters (length 64800, code rate 3/15) and modulation scheme (1024-symbol mapping). By tailoring the permutation sequence to match the specific system parameters, the interleaver achieves maximum error distribution effectiveness without requiring overly complex universal designs.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then error distribution effectiveness improves, but the system loses flexibility
Solution Approach 1:
The patent employs parameterized permutation orders that can be adapted to different LDPC code lengths, code rates, and modulation schemes. The interleaver design uses configurable parameters such as the number of bit groups and the specific permutation sequence, allowing it to be optimized for specific configurations while maintaining the ability to adapt to other configurations through parameter adjustment rather than structural redesign.
3Reliability
If burst errors are not distributed, then the system structure remains simple, but error correction performance degrades rapidly
Solution Approach 1:
By segmenting the codeword into bit groups and applying permutation to each group, the patent achieves effective error distribution where burst errors are scattered across multiple groups. This segmentation approach provides robust error correction performance while keeping the computational complexity of each individual group manageable and suitable for practical implementation.
Solution Approach 2:
The patent applies the permutation operation in advance during the encoding process, before transmission. This preliminary interleaving action ensures that when burst errors occur during transmission, they are already distributed across different bit groups, allowing the LDPC decoder to correct them effectively without requiring complex post-reception processing.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.