LDPC Bit Interleaving for 16-Symbol Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 2/15, using a specific permutation order for bit group-based interleaving, is designed to effectively distribute burst errors, compatible with next-generation broadcasting systems like ATSC 3.0, and integrated with a modulator performing 16-symbol mapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The bit interleaver divides the LDPC codeword into multiple bit groups (180 groups of 360 bits each) and applies permutation to each group independently. This segmentation allows the interleaver to effectively distribute burst errors across different bit groups while maintaining a manageable structure that doesn't overly complicate the system design
Solution Approach 2:
The interleaver uses specific permutation orders (such as the provided sequence of 180 integers) that are optimized for the given LDPC code parameters (length 64800, code rate 2/15) and modulation scheme (16-QAM). By changing the permutation parameters to match the specific system configuration, the interleaver achieves optimal error distribution without requiring a completely complex redesign
2Reliability
If the bit interleaver is optimized for specific LDPC parameters and modulation order, then performance is improved, but adaptability to different configurations is reduced
Solution Approach 1:
The interleaver design uses parameterized permutation orders that can be adjusted based on the specific LDPC code length, code rate, and modulation order being used. The same basic interleaver structure with 180 bit groups of 360 bits can be adapted to different configurations by changing the permutation sequence parameters, allowing optimization for each specific case while maintaining the same fundamental architecture
Solution Approach 2:
The bit interleaver structure is designed to be universally applicable to different LDPC codes and modulation schemes by using a standardized bit group organization (180 groups of 360 bits) that can accommodate various code rates and lengths. The permutation orders can be selected or generated to match different system requirements, making the same interleaver framework versatile across multiple configurations
Data Source
AI summary
A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.