LDPC Interleaving Layout for Faster 5G NR De-Interleaving
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Solution Overview
Problem
Current algorithms for de-interleaving and rate de-matching in LDPC decoding processes are inefficient, particularly due to the need for modulo operations and sequential processing, which increases CPU cycles and is not suitable for the shorter slot times of 5G wireless standards.
Innovation Solution
Implementing vector-based parallelization for de-interleaving and eliminating modular operations by pre-calculating start and wraparound positions for rate matching, allowing bulk memory operations and reducing the need for division operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential processing with modulo operations is used for de-interleaving and rate de-matching, then processing accuracy is maintained, but processing speed is too slow for 5G slot times
Solution Approach 1:
The patent divides the de-interleaving and rate de-matching operations into parallel segments that can be processed simultaneously. Instead of sequential processing, multiple processing units work on different portions of the data in parallel, eliminating the need for slow modulo operations while maintaining accuracy.
Solution Approach 2:
The patent transitions from one-dimensional sequential processing to multi-dimensional parallel processing by organizing data in multi-dimensional arrays and processing along different dimensions simultaneously. This dimensional transformation enables vector-based parallelization that achieves the required processing speed for 5G slot times.
2Productivity
If vector-based parallelization is implemented for de-interleaving, then processing speed increases 40 times, but implementation complexity increases
Solution Approach 1:
The patent performs preliminary organization of data into vector formats and pre-calculates certain parameters before the main processing stage. This preliminary preparation simplifies the subsequent parallel processing operations and reduces the overall implementation complexity despite the increased processing power required.
Solution Approach 2:
The patent designs a universal vector-based processing framework that can handle multiple operations (de-interleving, rate de-matching, and other LDPC operations) using the same parallel processing infrastructure. This multi-functionality reduces implementation complexity by avoiding separate specialized circuits for each operation.
3Loss of time
If pre-calculated start and wraparound positions are used for rate matching, then division operations are eliminated, but memory requirements increase
Solution Approach 1:
The patent pre-calculates and stores start and wraparound positions in lookup tables before the main processing occurs. This preliminary calculation eliminates the need for time-consuming division operations during real-time processing, trading off some memory usage for significant CPU cycle reduction.
Solution Approach 2:
The patent creates compact copies of essential parameters (start positions, wraparound positions) in fast memory or registers that can be quickly accessed during processing. These copied values replace complex division operations, reducing CPU cycles while minimizing the actual memory overhead through efficient data representation.
Data Source
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AI summary
Apparatuses and methods are disclosed for a communication device associated with a wireless transmission. In one embodiment, a method includes performing one of a low-density parity check, LDPC, decoding process and an LDPC encoding process by loading a set of bits, in parallel, into a plurality of registers, the set of bits being distributed among the plurality of registers; one of de-interleaving and interleaving the loaded set of bits within the plurality of registers by rearranging the loaded set of bits into one of a de-interleaved and an interleaved set of bits; and after the set of bits is rearranged into the one of the de-interleaved and the interleaved set of bits within the plurality of registers, writing the one of the de-interleaved and the interleaved set of bits, in parallel, from the plurality of registers to memory.