LDPC Bit Interleaving for 64-Symbol Burst-Error Spreading

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Solution Overview

Problem

Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.

Innovation Solution

A bit interleaver optimized for an LDPC coder with a length of 16200 and code rate of 4/15, using 64-symbol mapping, which interleaves the LDPC codeword on a bit group basis with a specific permutation order to effectively distribute burst errors, suitable for next-generation broadcasting systems like ATSC 3.0.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors occur and cause rapid performance degradation

Engineering Contradiction:
Improveperformance stabilityVSAvoidinterleaver design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the LDPC codeword into multiple bit groups (e.g., 45 bit groups of 360 bits each) and applies separate interleaving operations to each group using different permutation orders. This segmentation allows the system to distribute burst errors across different bit groups, preventing concentration of errors in any single group, thereby improving reliability without requiring a completely complex new structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different permutation orders to different bit groups, creating local variations in interleaving patterns. This local quality approach ensures that burst errors affecting one region do not systematically impact all regions, as each bit group experiences a unique interleaving pattern optimized for its position, thus enhancing performance stability

Inventive Principle:
Principle #3Local quality

2Reliability

If the bit interleaver is optimized for specific LDPC parameters and modulation order, then performance improves, but the adaptability to different configurations decreases

Engineering Contradiction:
Improveerror distribution effectivenessVSAvoidconfiguration flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent optimizes specific parameters such as bit group size (360 bits), number of bit groups (45), and permutation orders for the given LDPC code rate (4/15) and modulation scheme (64-NUC). These parameter changes are carefully selected to achieve optimal error distribution for the target configuration, maximizing reliability for this specific application scenario

Inventive Principle:
Principle #35Parameter changes

3Reliability

If burst errors are not distributed, then the system structure remains simple, but performance degrades rapidly in broadcast channels

Engineering Contradiction:
Improvetransmission reliabilityVSAvoidinterleaving structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies bit group-based interleaving with specific permutation orders before modulation to preemptively distribute potential burst errors. By performing this interleaving action in advance, the system prepares the codeword to withstand channel impairments, ensuring that even if burst errors occur during transmission, they will be distributed across multiple bit groups rather than concentrated, thus maintaining transmission reliability

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9800268B2Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 64-symbol mapping, and bit interleaving method using same
Publication Date: 2017.10.24 ELECTRONICS & TELECOMM RES INST
  • US9800268B2 patent drawing
  • US9800268B2 patent drawing
  • US9800268B2 patent drawing

AI summary

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.