LDPC Interleaving and Bit Mapping for Better Broadcast Decoding
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Solution Overview
Problem
There is a need for improved decoding and receiving performance in digital broadcasting services, particularly in high-quality digital televisions and portable multimedia players, due to the increasing demand for efficient methods to support various receiving methods of digital broadcasting services.
Innovation Solution
A transmitting apparatus and method that includes an encoder for generating an LDPC codeword, an interleaver for rearranging bit groups, and a modulator that maps bits from the LDPC codeword onto modulation symbols, utilizing a parity interleaver, group interleaver, and block interleaver to enhance decoding and receiving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional encoding and modulation methods are used, then device complexity is reduced, but decoding and receiving performance deteriorates
Solution Approach 1:
The interleaver is divided into three independent sub-interleavers: a parity interleaver that processes parity bits, a group interleaver that rearranges bit groups, and a block interleaver that performs block-wise interleaving. This segmentation allows each component to perform a specific function, improving overall decoding performance while keeping individual components manageable in complexity.
Solution Approach 2:
The patent introduces a multi-dimensional interleaving approach by combining row-wise and column-wise interleaving operations across different stages. The group interleaver operates on bit groups in one dimension, while the block interleaver operates on blocks in another dimension, creating a multi-layered interleaving structure that enhances performance without linearly increasing complexity.
2Reliability
If bit groups are interleaved and mapped according to the patent method, then decoding performance is improved, but processing time increases
Solution Approach 1:
The parity interleaver performs preliminary interleaving of parity bits before the main group and block interleaving operations. By pre-organizing the parity bit structure, the subsequent decoding process can more efficiently locate and process parity information, reducing overall processing time despite the additional interleaving stage.
Solution Approach 2:
Different interleaving strategies are applied to different parts of the codeword: parity bits receive specialized interleaving treatment through the parity interleaver, while information bits are processed through the group and block interleavers. This localized optimization allows critical parity information to be processed more efficiently, balancing performance improvement with processing time constraints.
Data Source
AI summary
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.