LDPC Interleaving Layout for Burst-Error-Resistant Decoding

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Solution Overview

Problem

In data transmission using LDPC codes, securing good communication quality is challenging due to errors and burst errors, which degrade decoding performance and increase power consumption in reception apparatuses.

Innovation Solution

A data processing apparatus and method that encodes information bits into LDPC codes with a specific code length and rate using a parity check matrix, and decodes received LDPC codes to improve error resistance and decoding performance by employing a parity interleaver and column twist interleaver to separate variable nodes connected to the same check node, thereby enhancing resistance to burst errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LDPC code with code length of 16200 bits and code rate of 12/15 is used, then error correction ability is improved, but device complexity increases due to large parity check matrix

Engineering Contradiction:

Improveerror correction abilityVSAvoidparity check matrix complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the large parity check matrix into multiple sub-matrices (information matrix portion and parity matrix portion) with specific structures. The information matrix portion uses a quasi-cyclic structure with smaller sub-matrices, and the parity matrix portion uses a staircase structure, making the overall large matrix manageable through modular segmentation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the structural parameters of the parity check matrix by defining specific patterns for the information matrix portion (using initial value tables with quasi-cyclic structure) and parity matrix portion (using staircase structure), transforming the complex matrix into a more manageable form with regular patterns.

Inventive Principle:

Principle #35Parameter changes

2Ease of operation

If conventional LDPC decoding is used, then decoding process is simple, but power consumption increases under burst error conditions

Engineering Contradiction:

Improvedecoding process simplicityVSAvoidpower consumption

Core Design Contradiction:

Ease of operationVSUse of energy by moving object

Solution Approach 1:

The patent performs preliminary actions by reordering bits using parity interleaver and column twist interleaver before decoding. This preprocessing rearranges the bit sequence to separate variable nodes connected to the same check node, making the decoding process more efficient under burst error conditions and reducing the number of iterations needed, thereby lowering power consumption.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If variable nodes connected to the same check node are kept together, then decoding computation is efficient, but resistance to burst errors deteriorates

Engineering Contradiction:

Improvedecoding computation efficiencyVSAvoidresistance to burst errors

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies the opposite approach by deliberately separating variable nodes that would normally be connected to the same check node through interleaving operations. This inversion of the conventional grouping strategy improves burst error resistance while maintaining acceptable decoding efficiency through the structured parity check matrix design.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS11082065B2Data processing apparatus and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio

Publication Date: 2021.08.03 SATURN LICENSING LLC

AI summary

The present technology relates to a data processing apparatus and a data processing method that are able to provide an LDPC code with a good error rate.An LDPC encoder performs coding by an LDPC code having a code length of 16200 bits and a code rate of 12/15. The LDPC code includes an information bit and a parity bit, and a parity check matrix H is configured with an information matrix portion corresponding to the information bit of the LDPC code and a parity matrix portion corresponding to the parity bit. An information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table representing a position of an element of 1 in the information matrix portion at an interval of 360 columns. The present technology may be applied to a case of performing an LDPC coding and an LDPC decoding.