LDPC Bit Interleaving for Burst-Error-Tolerant 64-Symbol Mapping
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 2/15, using 64-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis, with a specific permutation order, and integrated into a BICM device for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The bit interleaver divides the LDPC codeword into multiple bit groups and applies different permutation patterns to different segments. This segmentation allows the system to handle burst errors more effectively by distributing them across different code blocks, thereby improving reliability without requiring a complete redesign of the entire interleaving system.
Solution Approach 2:
The patent applies different permutation patterns (first, second, and third patterns) to different portions of the codeword based on local requirements. Specifically, different bit groups undergo different permutation operations, allowing the system to optimize error distribution locally while maintaining overall system performance.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then performance is maintained, but the device complexity increases
Solution Approach 1:
The patent employs multiple permutation patterns that can be selected and applied based on specific modulation orders (e.g., 64-QAM) and code parameters (LDPC codeword length of 64800, code rate of 2/15). By changing the permutation parameters according to the operating conditions, the system maintains optimal performance without requiring a completely different interleaver structure for each scenario.
3Reliability
If burst errors are not distributed, then the interleaver structure remains simple, but error correction performance degrades rapidly
Solution Approach 1:
Instead of trying to protect against burst errors directly, the patent inverts the approach by deliberately scrambling the original error pattern through multiple permutation patterns. This inversion transforms concentrated burst errors into dispersed errors that are more easily corrected by the LDPC decoder, thereby improving error distribution without requiring complex additional error correction mechanisms.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.