Group-Wise LDPC Interleaving for Burst-Error-Resilient Modulation

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Solution Overview

Problem

Current data transmission using LDPC codes faces challenges in maintaining excellent communication quality, particularly due to errors and erasures that affect decoding performance and increase power consumption in receiving devices.

Innovation Solution

The implementation of a data processing device and method that incorporates parity interleave and group-wise interleave techniques to improve error rates and tolerance against burst errors, using a transformed parity check matrix with a pseudo cyclic structure to separate variable nodes connected to the same check node, thereby enhancing decoding performance and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LDPC coding is used without adapted interleaving, then implementation is simpler, but communication quality and error correction performance deteriorate

Engineering Contradiction:
Improvecommunication qualityVSAvoidinterleaver structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interleaver is divided into multiple blocks, each processing a segment of the LDPC code. This segmentation allows the system to achieve excellent communication quality through structured bit permutation while maintaining manageable complexity by processing data in divided units rather than as a monolithic block.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interleaver parameters (block size, permutation patterns) are specifically adapted to match the LDPC code parameters (code length N=16200, rate 8/15). This parameter adaptation optimizes the interleaving process to enhance error correction performance while avoiding unnecessary complexity from generic or overly complex interleaving structures.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If code length is increased to approach Shannon limit, then error correction capability improves, but transmission time and latency increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidtransmission time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The bit interleaving is performed in advance on the LDPC code before transmission. This preliminary action optimizes the code structure to better withstand burst errors and channel impairments, enabling the system to achieve near-Shannon limit performance with the given code length N=16200 without requiring excessively long codes that would increase transmission time.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If standard interleaving is used, then implementation is straightforward, but tolerance against burst errors is insufficient

Engineering Contradiction:
Improveburst error toleranceVSAvoidinterleaving structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interleaver processes the LDPC code in segmented blocks with specific permutation patterns designed to disperse burst errors across multiple code words. This segmentation approach provides superior burst error tolerance by ensuring that consecutive errors do not concentrate on a single code word, while the modular block structure keeps implementation complexity manageable.

Inventive Principle:
Principle #1Segmentation

4Reliability

If more powerful error correction is implemented, then communication quality improves, but power consumption in receiving devices increases

Engineering Contradiction:
Improvedecoding performanceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The bit interleaving is performed at the transmitter before transmission, preparing the code structure to be more resilient to channel errors. This preliminary action reduces the decoding complexity and power consumption at the receiver, as the interleaved structure allows the LDPC decoder to correct errors more efficiently without requiring excessively powerful (and power-intensive) decoding algorithms.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3148091B1Bit interleaved coded modulation with a group-wise interleaver adapted to a rate 8/15 LDPC code of length 16200
Publication Date: 2021.03.10 SONY GROUP CORP
  • EP3148091B1 patent drawingFigure 1
  • EP3148091B1 patent drawingFigure 2
  • EP3148091B1 patent drawingFigure 3

AI summary

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.