Group-Wise LDPC Interleaving for Burst Error Tolerance

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Solution Overview

Problem

There is a demand to secure excellent communication quality in data transmission using Low Density Parity Check (LDPC) codes, which face challenges in maintaining decoding performance under burst errors and erasures, particularly in AWGN communication paths.

Innovation Solution

The implementation of a data processing device and method that employs a parity interleaver and group-wise interleaver to interleave parity bits, transforming the parity check matrix into a pseudo-cyclic structure, thereby improving tolerance against burst errors and maintaining decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LDPC coding is used without special interleaving, then decoding complexity is reduced, but error correction capability deteriorates under burst errors and erasures

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The code block is divided into multiple segments of 360 bits each, and interleaving is performed independently within each segment. This segmentation allows the system to maintain lower decoding complexity while improving error correction capability by distributing burst errors across different segments and check nodes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Parity bits are interleaved before encoding and mapping operations. This preliminary interleaving action ensures that burst errors and erasures are distributed across different check nodes before decoding, preventing simultaneous errors that would otherwise require more complex decoding algorithms.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If parity bits are not interleaved, then processing speed is maintained, but tolerance against burst errors deteriorates

Engineering Contradiction:
Improveburst error toleranceVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The interleaving operation is segmented into independent 360-bit units that can be processed in parallel. This segmentation maintains processing speed by enabling concurrent operations while still providing burst error tolerance through the distribution of errors across segments and check nodes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interleaving pattern uses specific parameter changes (shifting by segment length multiples) to distribute parity bits effectively. This parameter-based approach provides burst error tolerance with simple, efficient operations that maintain processing speed.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If variable nodes connected to the same check node are not separated, then interleaving complexity is reduced, but decoding performance under erasures deteriorates

Engineering Contradiction:
Improvedecoding performanceVSAvoidinterleaving complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

By segmenting the code block into 360-bit units and interleaving within each segment, variable nodes connected to the same check node are naturally separated. This segmentation achieves decoding performance improvement with relatively simple interleaving operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interleaving is performed as a preliminary action before encoding and mapping, which separates variable nodes connected to the same check node in advance. This preliminary separation improves decoding performance under erasures while keeping the interleaving complexity manageable through the segmented approach.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3148088B1Bit interleaved coded modulation with a group-wise interleaver adapted to a rate 12/15 LDPC code of length 16200
Publication Date: 2021.03.03 SONY GROUP CORP
  • EP3148088B1 patent drawingFigure 1
  • EP3148088B1 patent drawingFigure 2
  • EP3148088B1 patent drawingFigure 3

AI summary

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.