LDPC Group-Wise Interleaving for Burst-Error-Resistant Transmission

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Solution Overview

Problem

Current data transmission using LDPC codes faces challenges in maintaining excellent communication quality due to errors and burst errors, particularly in burst error-prone communication paths.

Innovation Solution

The implementation of a data processing device and method that includes LDPC encoding with a specific parity check matrix, group-wise interleaving, and mapping to 256 signal points, which involves a detailed interleaving sequence to improve error resistance and communication quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LDPC encoding is performed with standard parameters, then data transmission can be implemented, but communication quality deteriorates due to errors and burst errors in the transmission path

Engineering Contradiction:
Improvecommunication qualityVSAvoiderror rate
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies segmentation by dividing the LDPC code into multiple bit groups (e.g., 360 bits per group) and applying different interleaving operations to different segments. This allows selective protection of information bits and parity bits against burst errors, improving overall communication quality without requiring complete retransmission on error occurrence.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action through pre-defined interleaving patterns and parity check matrix structures that are designed beforehand to withstand burst errors. The specific interleaving sequence (0, 17, 2, 30, 12, 7, ...) and parity matrix configuration are predetermined to distribute burst error impacts across multiple code words, preventing catastrophic failures.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If group-wise interleaving is applied to protect against burst errors, then error resistance improves, but processing complexity increases

Engineering Contradiction:
Improveerror resistanceVSAvoidinterleaving complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the interleaving operation into manageable bit groups of 360 bits, making the complex interleaving process more tractable. Each group can be processed independently using pre-calculated permutation patterns, reducing the overall computational burden while maintaining burst error protection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent optimizes the interleaving parameters by selecting specific bit group sizes (360 bits) and predefined permutation sequences that balance error protection effectiveness with processing complexity. These parameters are tuned to achieve good burst error resistance without excessive computational requirements.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10396824B2Data processing device and data processing method
Publication Date: 2019.08.27 SATURN LICENSING LLC
  • US10396824B2 patent drawing
  • US10396824B2 patent drawing
  • US10396824B2 patent drawing

AI summary

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.