LDPC Code Structure With Interleaving for Burst Error Resilience
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Solution Overview
Problem
In data transmission using LDPC codes, ensuring favorable communication quality is challenging due to issues like burst errors and erasures, which degrade decoding performance and increase power consumption.
Innovation Solution
The implementation of a transmission and reception system that employs LDPC codes with a dual diagonal structure parity matrix and interleaving techniques, such as parity interleaving and block interleaving, to improve error resilience and decoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC codes are used for data transmission, then error correction capability is provided, but communication quality deteriorates under burst errors and erasures
Solution Approach 1:
The patent applies segmentation by dividing the code structure into specific sections with dual diagonal parity matrices, creating structured LDPC codes that can better handle burst errors. The code is segmented into information bits and parity bits with specific positioning rules that enhance error resilience.
Solution Approach 2:
The patent changes parameters by defining specific code lengths (69120 bits) and rates (7/16 and 8/16) with dual diagonal parity matrix structures. These parameter modifications optimize the code for better performance under burst errors and erasures while maintaining compatibility with existing systems.
2Reliability
If LDPC decoding is performed to ensure error correction, then communication reliability improves, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-structuring the LDPC code with dual diagonal parity matrices and specific interleaving patterns before transmission. This pre-organization enables more efficient decoding processes that require fewer iterations and less computational power, thereby reducing energy consumption while maintaining high decoding performance.
3Reliability
If code length is increased to approach Shannon limit, then error correction performance improves, but system complexity increases
Solution Approach 1:
The patent changes parameters by establishing specific code lengths (69120 bits) and rates (7/16 and 8/16) that optimize the balance between error correction performance and system complexity. The dual diagonal parity matrix structure at these specific parameters provides near-Shannon-limit performance while maintaining manageable system complexity through regular patterns.
Solution Approach 2:
The patent applies composite materials concept by combining information bits and parity bits in a structured dual diagonal matrix format. This composite structure integrates multiple functional elements (error detection, correction, and efficiency optimization) into a unified code design that achieves high performance without proportionally increasing complexity.
Data Source
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AI summary
The present technique relates to a transmission apparatus, a transmission method, a reception apparatus, and a reception method that can ensure favorable communication quality in data transmission using an LDPC code. LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a code rate r of 7/16 or 8/16. The LDPC code includes information bits and parity bits, and the check matrix includes an information matrix corresponding to the information bits and a parity matrix corresponding to the parity bits. The information matrix is represented by a check matrix initial value table. The check matrix initial value table is a table indicating positions of elements of 1 in the information matrix on the basis of 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using the LDPC code.