LDPC Bit Interleaving Layout for 4096QAM Burst Error Resistance
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Solution Overview
Problem
Existing data transmission methods using LDPC codes face challenges in maintaining good communication quality due to errors and erasures, particularly in burst error environments, which affect decoding performance and power consumption.
Innovation Solution
The implementation of a transmission method that includes parity interleaving and block interleaving of LDPC codes, ensuring that parity bits are interleaved and distributed to prevent simultaneous errors at check nodes, thereby improving resistance to burst errors and maintaining decoding performance in additive white Gaussian noise (AWGN) channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity interleaving and block interleaving are applied to LDPC codes, then resistance to burst errors is improved, but device complexity increases
Solution Approach 1:
The interleaving process is divided into two distinct stages: parity interleaving that operates on parity bits within code blocks, and block interleaving that operates on groups of code bits. This segmentation allows each interleaver to be designed and implemented independently, managing complexity while achieving comprehensive burst error protection
Solution Approach 2:
The patent introduces an intermediate processing stage where parity bits are separately identified and interleaved before the main block interleaving operation. This intermediary step acts as a mediator that prepares the data in a specific format, enabling the subsequent block interleaver to operate more efficiently and achieve better error correction performance
2Reliability
If parity bits are interleaved and distributed to prevent simultaneous errors, then decoding performance is improved, but processing time increases
Solution Approach 1:
Parity bits are interleaved with information bits before the LDPC encoding process completes. This preliminary action ensures that when burst errors occur during transmission, the errors are already distributed across different check nodes, allowing the decoder to process errors more efficiently and reduce overall processing time
Solution Approach 2:
The interleaving pattern is specifically designed to distribute parity bits to different check nodes rather than uniformly distributing all bits. This local quality approach targets the specific requirement of LDPC decoding by ensuring that parity information available at each check node is optimally distributed, improving decoding performance without requiring excessive processing time
3Reliability
If check nodes receive distributed parity bits, then error correction capability is improved, but power consumption increases
Solution Approach 1:
The interleaving pattern changes the distribution parameters of parity bits to check nodes, creating a more favorable error distribution pattern. This parameter change in bit distribution allows the decoder to achieve better error correction capability with fewer iterative decoding steps, thereby reducing overall power consumption in the reception device
Data Source
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AI summary
The present technology relates to a transmission method and a reception device capable of ensuring good communication quality in data transmission by using an LDPC code. In group-wise interleaving, an LDPC code with a code length N of 69120 bits is interleaved in units of bit groups of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code after the group-wise interleaving is returned to an original arrangement. The present technology can be applied, for example, to the case of performing data transmission by using an LDPC code or the like.