LDPC Group-Wise Interleaving for Error Floor Reduction
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Solution Overview
Problem
Current data transmission using LDPC codes faces challenges in maintaining high communication quality, particularly in ensuring error correction and minimizing the error floor phenomenon in decoding characteristics.
Innovation Solution
A data processing device and method that performs LDPC coding with a specific parity check matrix, group-wise interleaving, and mapping to signal points, optimizing the LDPC code length and coding rate to enhance transmission quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC coding is used with conventional parameters, then error correction capability is provided, but communication quality and reliability are insufficient
Solution Approach 1:
The patent applies parameter changes by optimizing specific LDPC code parameters including code length (N=64800 bits), coding rate (r=11/15), and bit group size (360 bits). These parameter modifications enhance error correction capability and communication quality while maintaining system compatibility with existing LDPC frameworks.
Solution Approach 2:
The patent implements segmentation through group-wise interleaving that divides the LDPC code into bit groups of 360 bits each. This segmentation approach processes the code in manageable units, improving decoding performance and reducing the error floor phenomenon while maintaining overall code structure integrity.
2Reliability
If group-wise interleaving with bit group size of 360 bits is applied, then error floor phenomenon is minimized, but processing complexity increases
Solution Approach 1:
The patent optimizes the bit group size parameter to 360 bits for group-wise interleaving. This specific parameter value has been determined to minimize the error floor phenomenon in decoding characteristics while balancing processing complexity, achieving superior error correction performance compared to conventional interleaving approaches.
3Reliability
If LDPC code length is increased to improve error correction, then performance approaches Shannon limit, but transmission time and latency increase
Solution Approach 1:
The patent sets the LDPC code length to 64800 bits, which provides excellent error correction capability approaching the Shannon limit. This parameter is optimized to achieve high reliability while managing transmission time through efficient encoding and decoding processes.
Solution Approach 2:
By dividing the 64800-bit code into 360-bit groups for interleaving, the patent enables parallel processing capabilities that reduce overall transmission time and latency while maintaining the benefits of the long code length for error correction.
Data Source
AI summary
The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes.In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.