LDPC Group-Wise Interleaving and Mapping for Error Floor Reduction
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Solution Overview
Problem
Current data transmission using LDPC codes faces challenges in maintaining high communication quality, particularly in ensuring reliable error correction and minimizing the error floor phenomenon in decoding characteristics.
Innovation Solution
A data processing device and method that performs LDPC coding with a parity check matrix of 64800 bits and a coding rate of 13/15, followed by group-wise interleaving and mapping to specific signal points, effectively addressing the communication quality issues by optimizing bit group interleaving and signal point mapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC coding with code length N=64800 bits is used to improve error correction capability, then block error probability characteristics improve, but device complexity increases
Solution Approach 1:
The 64800-bit LDPC code is divided into multiple bit groups of 360 bits each. This segmentation allows the complex coding operation to be broken down into smaller, more manageable units that can be processed more efficiently, reducing overall device complexity while maintaining the error correction capabilities of the full-length code.
2Reliability
If group-wise interleaving is applied to improve communication quality, then decoding performance improves, but processing time increases
Solution Approach 1:
The LDPC code bits are divided into groups of 360 bits, and group-wise interleaving is applied to these segments. This approach improves communication quality by distributing error patterns across different groups, while the segmented structure enables parallel processing that mitigates the time penalty associated with interleaving operations.
3Reliability
If mapping to specific signal points is optimized to reduce error floor phenomenon, then decoding characteristics improve, but mapping complexity increases
Solution Approach 1:
The patent applies specific mapping rules to different portions of the interleaved bit sequence, optimizing the mapping of information bits and parity bits to different signal point positions. This local optimization approach reduces the error floor phenomenon by ensuring that critical bits are mapped to more robust signal positions, while the structured nature of the mapping rules keeps implementation complexity manageable.
Data Source
AI summary
The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.