LDPC Codeword Interleaving and Mapping for Lower Receiving Threshold
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Solution Overview
Problem
Existing broadcast communication standards face challenges in achieving optimal performance for LDPC coding, bit interleaving, and constellation mapping, leading to higher receiving thresholds at the receiving end.
Innovation Solution
An interleaving and mapping method for LDPC codewords is developed, involving multiple bit interleaving steps, constellation mapping, and optimized permutation orders and constellation diagrams to reduce the receiving threshold, along with a deinterleaving and demapping method to improve system performance for different code rates and lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC coding, bit interleaving and constellation mapping are used independently, then system complexity is reduced, but receiving threshold increases and performance deteriorates
Solution Approach 1:
The patent combines LDPC coding, bit interleaving, and constellation mapping into a unified joint design framework. The interleaver and mapper are designed together rather than independently, creating an integrated system that optimizes overall performance. This merging resolves the contradiction by achieving lower receiving thresholds through coordinated design while managing complexity through a structured unified approach.
Solution Approach 2:
The patent optimizes multiple parameters including interleaver size, mapping constellation configuration, and code rate simultaneously. By adjusting these parameters together in a joint optimization framework, the system achieves lower receiving thresholds. The theoretical analysis provides guidance on parameter selection to balance performance improvement with computational complexity.
2Reliability
If targeted bit interleaving is designed through theoretical analysis and optimization, then receiving threshold is reduced, but design complexity increases
Solution Approach 1:
The patent performs theoretical analysis and optimization in advance to determine optimal interleaving patterns and mapping configurations for different channel conditions. These pre-computed parameters are then used during actual transmission without requiring complex real-time calculations. This preliminary action reduces the receiving threshold while keeping implementation complexity manageable.
Solution Approach 2:
The patent uses theoretical models and simulations to create optimized interleaving and mapping patterns that can be replicated in practical implementations. The theoretical analysis produces specific parameter sets and configuration patterns that can be copied and applied across different systems, reducing both receiving threshold and design complexity through reuse of proven configurations.
3Reliability
If joint optimization of LDPC coding, bit interleaving and constellation mapping is performed, then system performance is improved, but computational complexity increases
Solution Approach 1:
The patent divides the joint optimization problem into manageable segments: LDPC code design, interleaver design, and mapper design. Each segment can be optimized separately using targeted theoretical analysis, then integrated into a complete system. This segmentation allows for improved system performance while controlling computational complexity by breaking down the overall optimization task.
Solution Approach 2:
The patent creates a flexible joint optimization framework that can adapt to different channel conditions, code rates, and system requirements. The theoretical analysis provides dynamic parameter selection guidelines that allow the system to optimize performance for specific scenarios without requiring exhaustive optimization for all possible conditions. This dynamic approach improves performance while managing complexity through selective optimization.
Data Source
AI summary
An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving.