LDPC Error Correction With Adjustable Iteration Parameters
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Solution Overview
Problem
Conventional memory sub-systems are time and resource intensive due to the need to process each bit of the sense word twice during error correction, adding complexity and prolonging the error correction process.
Innovation Solution
Configuring iterative error correction parameters using criteria from previous iterations or implementing adjustable parameters after a threshold number of iterations, reducing the number of passes over each bit and optimizing the error correction process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction processes process each bit of the sense word twice during each iteration, then error correction reliability is improved, but processing time and computational complexity increase
Solution Approach 1:
The patent applies dynamics by making the number of passes per bit variable rather than fixed. In early iterations, multiple passes are performed to ensure reliable error detection and correction. In later iterations, the number of passes is reduced dynamically, allowing the system to maintain error correction reliability while reducing processing time as the correction process progresses.
Solution Approach 2:
The patent changes the parameter of passes per bit from a constant value (twice per bit) to a variable value that decreases over iterations. This parameter change allows the system to adapt the processing intensity based on the correction progress, maintaining reliability when needed while reducing time consumption as corrections are made.
2Reliability
If conventional error correction processes process each bit of the sense word twice during each iteration, then error correction thoroughness is improved, but device complexity increases
Solution Approach 1:
The patent reduces computational complexity by dynamically adjusting the number of passes per bit based on iteration number. Early iterations use multiple passes for thorough error detection, while later iterations use fewer passes, reducing the overall computational burden and device complexity required for the error correction process.
Solution Approach 2:
The patent applies partial action by performing multiple passes per bit only when necessary (in early iterations when errors are more likely), and reducing to single or fewer passes in later iterations when the data is already partially corrected. This avoids excessive processing while maintaining sufficient thoroughness for effective error correction.
3Productivity
If a fixed number of iterations is used for error correction, then processing speed is improved, but error correction capability deteriorates
Solution Approach 1:
The patent makes the error correction process adaptive by dynamically adjusting parameters such as the number of passes per bit based on the iteration number and correction progress. This allows the system to maintain high error correction capability throughout the process while optimizing processing speed by reducing intensive operations in later iterations when corrections are already underway.
Data Source
AI summary
A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.