LDPC Error Correction Circuit With Syndrome-Based Iteration Skipping
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Solution Overview
Problem
Current error correction decoding processes in memory systems are inefficient, requiring excessive time due to the iterative nature of low density parity check (LDPC) codes, which complicates the error correction process and increases computational complexity.
Innovation Solution
An error correction circuit and method that utilize a mapper to generate read values quantized into multiple levels, a node processing component for iterative decoding, and a global iteration control component to manage syndrome information and skip unnecessary iterations based on a defined policy, optimizing the decoding process within a maximum global iteration number.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative LDPC decoding is performed with multiple global iterations to improve error correction capability, then reliability is improved, but time required for decoding increases
Solution Approach 1:
The patent applies the skipping principle by introducing a global iteration skip policy that allows the decoder to skip certain intermediate global iterations (g+1)th to (G−1)th) when the syndrome information from the current g-th iteration already satisfies predefined conditions. This enables the system to rush through unnecessary iterations while maintaining error correction capability, thereby reducing decoding time without sacrificing reliability.
Solution Approach 2:
The patent implements feedback by continuously monitoring syndrome information after each global iteration and using this feedback to dynamically determine whether to continue or skip subsequent iterations. The syndrome information management component and global iteration control component work together to evaluate decoding progress and adjust the iteration schedule accordingly, creating a closed-loop control system that optimizes decoding time based on actual decoding status.
2Measurement precision
If multiple read voltages are used to generate quantized read values for improved decoding accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the read value quantization process into multiple stages corresponding to different numbers of read voltages (g=1, 2, ..., G). Each global iteration g uses g read voltages to generate read values quantized into g+1 levels, creating a segmented approach where complexity is distributed across iterations rather than requiring all complexity simultaneously. This allows progressive refinement of measurement precision while managing device complexity incrementally.
Data Source
AI summary
There are provided an error correction circuit and a method of operating the same. The circuit may performs error correction decoding within a maximum global iteration number G, and may include a mapper configured to generate read values quantized into g+1 levels to be used in a g-th global iteration by using read values corresponding to g number of read voltages, a node processing component configured to perform error correction decoding, during the g-th global iteration, by using the read values quantized into g+1 levels, a syndrome information management component configured to manage syndrome information corresponding to the g-th global iteration, and a global iteration control component configured to, when error correction decoding fails in the g-th global iteration, determine whether the syndrome information corresponding to the g-th global iteration satisfies a condition defined in a global iteration skip policy, and decide whether to skip (g+1)th to (G−1)th global iterations.