LDPC Convolutional Code Rate Switching With Known-Bit Insertion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current erasure correction codes face challenges in efficiently changing coding rates in response to varying communication quality, leading to increased circuit scales for encoders and decoders, which hampers transmission efficiency and erasure correction capability.
Innovation Solution
The method generates a low-density parity check convolutional code (LDPC-CC) with a coding rate of 1/3 by modifying parity check polynomials and inserting known information to adjust the coding rate, reducing the circuit scales of encoders and decoders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Reed-Solomon code block length is increased to improve correction capability, then erasure correction capability is improved, but computation amount and circuit scale increase
Solution Approach 1:
The patent changes the fundamental parameter of the error correction code from Reed-Solomon block code to LDPC convolutional code, which has different structural characteristics. LDPC-CC uses a sparse parity check matrix with time-varying periodicity, allowing flexible code rates without proportionally increasing circuit scale. The encoding uses simple modulo-2 addition operations that can be implemented with minimal hardware resources while maintaining strong error correction capability through iterative belief propagation decoding.
2Adaptability or versatility
If multiple encoders are prepared for different coding rates, then adaptability to communication quality is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic coding rate adjustment within a single LDPC-CC encoder by changing the coding rate parameter α (where 1/2 < α ≤ 1) and adjusting the time-varying period m accordingly. The encoder structure remains fixed, but the encoding behavior dynamically adapts to different channel conditions through parameter reconfiguration. This allows the system to switch between coding rates (e.g., 2/3, 3/4, 4/5) without physically changing the encoder hardware.
Solution Approach 2:
The patent enables coding rate adaptation by changing key parameters of the LDPC-CC code: the coding rate α and the time-varying period m. By adjusting these parameters, a single encoder can generate codes with different rates suitable for various communication qualities. The parity check polynomial coefficients are also adjusted based on these parameters, allowing flexible adaptation without multiple dedicated encoders.
3Productivity
If LDPC-CC with coding rate 1/3 is generated from coding rate 1/2, then transmission efficiency is improved, but encoding complexity increases
Solution Approach 1:
The patent segments the information bits into groups and processes them through the time-varying LDPC-CC encoder with period m=3. The segmentation allows the encoder to handle different coding rates by processing different numbers of information bits within each time period. For coding rate 1/3, the encoder processes information in a segmented manner that generates more parity bits relative to information bits, achieving higher transmission redundancy without requiring a fundamentally different encoding structure.
Solution Approach 2:
The patent creates a universal LDPC-CC encoder that can generate multiple coding rates (1/2, 1/3, and other rates between 1/2 and 1) using the same basic encoding structure. The encoder's universality is achieved through parameter configuration rather than structural modification. The same modulo-2 addition operations and shift register structure serve multiple coding rate functions, avoiding the need for separate encoding circuits for each rate.
Data Source
AI summary
An encoding method changes an encoding rate of an erasure correcting code. One cycle is defined as 12k bits (wherein k represents a natural number) which is an encoding output using LDPC-CC with an encoding rate of ½, and includes information and parity. From the one cycle, only the information is arranged in the output order of the encoding output to obtain 6k bit information X6i, X6i+1, X6i+2, X6i+3, X6i+4, X6i+5, . . . , X6(i+k−1) X6(i+k−1)+1, X6(i+k−1)+2, X6(i+k−1)+3, X6(i+k−1)+4, and X6(i+k−1)+5. Known information is inserted in 3k pieces of information (Xj) among the 6k bit information, so that when 3k pieces of mutually different j is divided by 3, there is a remainder of 0 regarding k pieces, there is a remainder of 1 regarding k pieces, and there is a remainder of 2 regarding k pieces, to thereby obtain the parity from the information containing the known information.