Latch-Based LDPC Decoder Pipelines for Low-Voltage Throughput
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Solution Overview
Problem
Low-Density Parity-Check (LDPC) decoders in communication systems face significant power requirements, especially in next-generation wireless communication systems with higher data rates, due to the computational complexity of maximum likelihood decoding and the need for efficient error correction.
Innovation Solution
Implementing a latch-based pipeline architecture for LDPC decoders, which allows for dynamic voltage scaling and reduced power consumption by exploiting time-borrowing between pipeline stages, thereby improving energy efficiency and reducing the need for voltage and timing guard bands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fully parallel LDPC decoder architecture is used to achieve high data rate decoding, then decoding speed and error correction performance are improved, but power consumption increases significantly
Solution Approach 1:
The decoder architecture is segmented into multiple pipeline stages, where each stage performs a specific portion of the decoding computation. This segmentation allows the system to process multiple codewords concurrently at different pipeline stages, achieving high throughput while distributing power consumption across stages that can be dynamically controlled
Solution Approach 2:
The patent employs periodic clock gating and dynamic voltage scaling across pipeline stages, activating only the necessary stages for current decoding operations. This periodic activation pattern reduces average power consumption while maintaining the ability to achieve peak decoding speeds when needed
2Reliability
If higher supply voltage is used to meet timing requirements in parallel pipelines, then decoding reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage and frequency scaling (DVFS) across different pipeline stages, allowing each stage to operate at the minimum voltage necessary to meet its timing requirements. This dynamic adjustment enables the system to achieve timing closure for critical paths while reducing overall power consumption by operating non-critical stages at lower voltages
Solution Approach 2:
The system changes operational parameters (voltage, frequency) of different pipeline stages based on their specific timing requirements and workload. By adjusting these parameters dynamically, the system achieves reliable timing closure where needed while minimizing power consumption in less critical paths
3Productivity
If more pipeline stages are added to increase throughput, then decoding capacity is improved, but device complexity increases
Solution Approach 1:
The patent designs pipeline stages with universal, reusable components that can be instantiated multiple times. Each pipeline stage uses the same core decoding logic and data structures, allowing the system to increase throughput by replicating proven stages rather than designing increasingly complex unique stages, thereby controlling device complexity
Data Source
AI summary
A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.