LDPC Decoder Layer Processing With Distributed Check Node Units
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Solution Overview
Problem
Low density parity check (LDPC) decoders face complexity in interconnect issues and require efficient memory and logic resources for effective error correction in communication and data storage systems.
Innovation Solution
The implementation of novel techniques for decoding LDPC codes, including a check node unit (CNU) with comparators for comparing stored minimum values to a received variable message, and a method for processing LDPC codes using log-likelihood ratios and cyclic shifts, which reduces message storage memory and routing logic, and enables block parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional LDPC decoder is implemented with full interconnect structure, then error correction capability is maintained, but device complexity and interconnect issues increase
Solution Approach 1:
The decoder is divided into multiple check node units (CNUs), each responsible for processing a specific subset of parity check equations. Each CNU contains a reduced set of comparators corresponding only to its assigned equations, eliminating the need for full interconnect structure while maintaining error correction capability through distributed processing
Solution Approach 2:
The patent introduces a dimensional organization where CNUs are arranged in an array structure with each unit handling a specific dimension (subset) of the parity check matrix. This spatial segmentation across multiple dimensions allows the system to maintain computational completeness while reducing individual unit complexity and interconnect requirements
2Measurement precision
If more memory resources are allocated for message storage, then decoding accuracy is improved, but device complexity and resource requirements increase
Solution Approach 1:
Each check node unit is equipped with a local memory structure containing only the comparators and storage elements necessary for processing its specific subset of parity check equations. This localized resource allocation ensures each unit has sufficient memory for its designated function while avoiding the overhead of providing full memory resources across the entire decoder system
Solution Approach 2:
The message storage memory is segmented and distributed across multiple CNUs rather than using a centralized large memory structure. Each CNU maintains its own compact memory for storing relevant message values, reducing total memory requirements while maintaining decoding accuracy through distributed storage and processing
Data Source
AI summary
A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order.