LDPC Layer Scheduling for Faster Convergence and Lower Decoding Complexity

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Solution Overview

Problem

Current communication systems face challenges in efficiently decoding low-density parity-check (LDPC) codes due to high decoding complexity and error correction requirements, especially in noisy channels, which affects the reliability and speed of data transmission in next-generation mobile communication systems.

Innovation Solution

The proposed solution involves a method and device for improving LDPC code decoding performance by applying appropriate layer scheduling based on the structural, algebraic, and analytical characteristics of the LDPC code, using sub-sequential layered scheduling, which identifies a parity check matrix and a first layer scheduling sequence to perform layered decoding, reducing complexity and enhancing error-correction performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LDPC decoding methods are used, then error correction capability is maintained, but decoding complexity is high and convergence speed is slow

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The parity check matrix H is divided into multiple row blocks, where each row block corresponds to a separate layer. This segmentation allows the decoding process to be distributed across multiple layers, reducing the computational complexity of each individual layer while maintaining the overall error correction capability of the complete matrix.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic layer scheduling that adapts the decoding order and structure based on the specific characteristics of the parity check matrix. The layer scheduling sequence is determined dynamically to optimize convergence speed, allowing the system to adapt to different channel conditions and code rates while maintaining efficient decoding performance.

Inventive Principle:
Principle #15Dynamics

2Reliability

If conventional LDPC decoding methods are used, then error correction capability is maintained, but convergence speed is slow

Engineering Contradiction:
Improveerror correction capabilityVSAvoidconvergence speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent performs preliminary analysis of the parity check matrix structure to determine an optimal layer scheduling sequence before decoding begins. By pre-organizing the row blocks into layers based on their structural characteristics and dependencies, the system prepares an optimized decoding path that accelerates convergence while ensuring complete error correction capability is achieved.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The layer scheduling mechanism dynamically adjusts the decoding process based on the specific parity check matrix being used. Different scheduling sequences are applied depending on the matrix structure, allowing the system to optimize convergence speed for each specific code configuration while maintaining reliable error correction performance.

Inventive Principle:
Principle #15Dynamics

3Ease of operation

If standard decoding approaches are used, then implementation is straightforward, but decoding efficiency is low

Engineering Contradiction:
Improveimplementation simplicityVSAvoiddecoding efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

By segmenting the parity check matrix into row blocks that form distinct layers, the patent creates a structured approach that is both systematic and efficient. Each layer can be processed independently with clear data flow between layers, making the implementation straightforward while significantly improving decoding efficiency through parallel processing capabilities and reduced computational redundancy.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250096941A1Layered decoding method and apparatus for low density parity check code in communication system
Publication Date: 2025.03.20 SAMSUNG ELECTRONICS CO LTD
  • US20250096941A1 patent drawing
  • US20250096941A1 patent drawing
  • US20250096941A1 patent drawing

AI summary

A decoding method performed by a receiver of a communication system, according to an embodiment, comprises: receiving a signal transmitted from a transmitter; identifying a parity check matrix for decoding the signal; identifying a first layer scheduling sequence corresponding to the parity check matrix; and performing layered decoding on the basis of at least a part of the parity check matrix and at least a part of the first layer scheduling sequence.