Layered LDPC Decoder Scheduling to Minimize Idle Cycles
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Solution Overview
Problem
Low-Density Parity-Check (LDPC) coding techniques face challenges in practical exploitation due to routing congestion and memory collisions, limiting the effectiveness of parallelism in decoding algorithms, despite advancements in joint code-decoder design and layered decoding schedules.
Innovation Solution
The implementation of a Horizontal Layered Schedule (HLS) decoding method for LDPC codes, which optimizes the sequence of layers to minimize idle cycles through a cost function, allowing for efficient serial processing and synchronization of processing units, thereby reducing latency and enhancing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If joint code-decoder design techniques are used to vectorize the decoder architecture, then parallelism is improved and iteration latency is reduced, but memory collision and routing congestion occur limiting practical exploitation
Solution Approach 1:
The decoder architecture is segmented into multiple independent processing units that operate in parallel on different segments of the parity-check matrix. Each processing unit handles a specific subset of rows without interfering with others, eliminating memory collision and routing congestion while maintaining high parallelism for improved decoding throughput.
2Productivity
If more than P processing units are used in parallel to achieve higher throughput, then decoding speed is improved, but complexity overhead and latency overhead increase significantly
Solution Approach 1:
The patent employs exactly P processing units where P matches the block structure size of the LDPC code, achieving optimal parallelism without excessive resources. This partial action approach processes P rows simultaneously in each iteration, providing sufficient throughput for high-speed applications while avoiding the complexity overhead associated with using more than P units.
3Reliability
If the sequence of layers is optimized through off-line computer simulations, then error correction capability and convergence speed are improved, but no systematic optimization algorithm is provided
Solution Approach 1:
The patent performs preliminary optimization of the layer sequence through off-line computer simulations to identify the optimal ordering that maximizes error correction capability and convergence speed. This preliminary action establishes a fixed optimal sequence that is then implemented in the hardware architecture, providing systematic optimization without adding runtime complexity to the decoder operation.
Data Source
AI summary
An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for a current layer are pipelined with acquisition of input data for a next layer, whereby the current layer and the next layer may attempt to use soft output information common to both layers. The serial processing unit is configured for delaying acquisition of input data for the next layer over a number of idle clock cycles. Latency due to the idle clock cycles is minimized by selectively modifying the sequence of layers through the decoding process and the sequence of messages processed by a certain layer.