LDPC Layered Decoding Scheduling for Faster Error Correction

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Solution Overview

Problem

Existing LDPC decoding methods, such as flooding scheduling, are inefficient in terms of convergence speed and decoding performance, particularly in error correction for data stored on storage media like hard disk drives or flash drives.

Innovation Solution

Implementing a selective layered decoding scheduling technique that uses a cost function to prioritize the processing of check nodes, selecting groups based on evaluated cost functions to optimize error correction decoding, ensuring that check nodes are processed in a manner that minimizes the number of iterations required to achieve successful decoding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If flooding scheduling is used for LDPC decoding, then the decoding process is simple to implement, but the convergence speed is slow and decoding performance deteriorates

Engineering Contradiction:
Improveimplementation simplicityVSAvoidconvergence speed
Core Design Contradiction:
Ease of operationVSSpeed

Solution Approach 1:

The patent applies dynamics by transitioning from static flooding scheduling to dynamic layered decoding scheduling. The check nodes are organized into multiple layers, and the processing order between layers is dynamically adjusted based on decoding progress and error patterns, allowing the system to adaptively optimize convergence speed while maintaining implementation feasibility

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent segments the check nodes into multiple layers (first layer, second layer, etc.) rather than processing them all simultaneously as in flooding scheduling. This segmentation enables controlled information flow between layers, improving convergence speed by ensuring proper message passing sequence while keeping each layer's processing relatively simple

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If flooding scheduling is used for LDPC decoding, then the implementation is straightforward, but decoding performance deteriorates particularly when errors persist in later groups

Engineering Contradiction:
Improveimplementation easeVSAvoiddecoding performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements dynamic scheduling where the processing order of check node layers is adjusted based on decoding performance and error patterns. When errors persist in later groups, the scheduler can reprocess affected layers, improving reliability without requiring complete redesign of the decoding architecture

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent incorporates feedback mechanisms where decoding results from one layer inform the processing of subsequent layers. The scheduler uses information about which check nodes have been satisfied and which remain unsatisfied to adjust the processing sequence, thereby improving decoding performance while maintaining implementation ease

Inventive Principle:
Principle #23Feedback

3Device complexity

If traditional LDPC decoding methods are used, then the processing order is fixed, but the time required for error correction decoding increases

Engineering Contradiction:
Improveprocessing order structureVSAvoiddecoding time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent replaces the fixed processing order with a dynamic scheduling approach where check node layers are processed in an optimized sequence based on current decoding state. This dynamic reordering reduces unnecessary iterations and decreases decoding time while maintaining a structured layer-based framework that does not excessively increase device complexity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent performs preliminary organization of check nodes into layers with defined processing sequences before actual decoding begins. This preliminary structuring enables more efficient error correction by pre-positioning critical check node processing earlier in the sequence, reducing overall decoding time without adding significant complexity

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8918696B2Implementation of LDPC selective decoding scheduling
Publication Date: 2014.12.23 SK HYNIX MEMORY SOLUTIONS AMERICA INC
  • US8918696B2 patent drawing
  • US8918696B2 patent drawing
  • US8918696B2 patent drawing

AI summary

A method for decoding data is disclosed. The method includes partitioning a low-density parity check (LDPC) matrix into a plurality of groups, each comprising one or more check node layers. The method further includes selecting one of the groups based at least in part on a cost function, the cost function based at least in part on information associated with a variable node, or information associated with a check node, or both. The method further includes performing LDPC layered decoding on the selected group.