Layered LDPC Decoder Parallelism for Throughput-Latency Tradeoffs
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Solution Overview
Problem
Current LDPC decoding techniques face challenges in achieving high throughput while maintaining low power consumption, especially in battery-powered devices, due to high computational complexity and increased hardware requirements for supporting emerging wireless standards.
Innovation Solution
The Parallel Processing Layered (PPL) technique reduces computational complexity by using multiple processors to perform LDPC decoding on Z-grouped rows of an H-matrix in sub-iterations, processing rows in different directions, and employing a Scaled Min-Sum decoding approach to decrease the number of iterations required for convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors are used to perform LDPC decoding on Z-grouped rows of H-matrix in parallel, then decoding throughput is improved, but device complexity and power consumption increase
Solution Approach 1:
The H-matrix is divided into Z-grouped rows that can be processed independently in parallel by multiple processing elements. Each processing element handles a specific subset of rows, enabling parallel decoding operations while maintaining manageable complexity for each individual processor.
Solution Approach 2:
The patent introduces a new dimension of parallel processing by organizing the decoding process into multiple sub-iterations, where different processing elements work on different rows simultaneously. This multi-dimensional parallelism (both across processing elements and across sub-iterations) increases throughput without requiring each processor to handle the entire matrix.
2Productivity
If multiple processors are used to perform LDPC decoding on Z-grouped rows of H-matrix in parallel, then decoding throughput is improved, but power consumption increases
Solution Approach 1:
The decoding workload is segmented across multiple processing elements that operate independently on different row groups. This segmentation allows the system to achieve high throughput through parallelism while each individual processing element consumes less power, and the overall system can manage power consumption by controlling the number of active processing elements.
Solution Approach 2:
The patent employs multiple sub-iterations where processing elements are activated in a periodic manner across different sub-iterations. Rather than all processors running continuously, they operate in staggered phases, which reduces peak power consumption while maintaining high average throughput through the parallel execution across sub-iterations.
3Device complexity
If conventional LDPC decoding is used, then implementation is simple, but decoding latency is high
Solution Approach 1:
The H-matrix is segmented into Z-grouped rows that can be processed independently and in parallel. This segmentation enables multiple processing elements to work simultaneously on different portions of the matrix, significantly reducing the overall decoding time and latency while maintaining implementation simplicity through the modular structure.
Solution Approach 2:
The patent performs preliminary organization of the H-matrix into Z-grouped rows that are pre-configured for parallel processing. This preliminary structuring allows processing elements to immediately begin parallel decoding operations without complex coordination overhead, reducing latency while keeping the implementation approach simple and systematic.
Data Source
AI summary
According to one embodiment, a wireless communications device includes a low-density parity check (LDPC) decoder configured to receive a codeword associated with a parity check H-matrix. The LDPC decoder includes multiple processing elements coupled to a memory for storing the parity check H-matrix comprising R rows and C columns. Each processing element is configured to perform LDPC decoding on different rows of the H-matrix during multiple sub-iterations. A first portion of the processing elements are configured to process certain rows in an upward direction in the H-matrix relative to other rows and a second portion of the processing elements are configured to process other certain rows in a downward direction in the H-matrix relative to the other rows.