LDPC Decoder Memory Mapping for Buffer-Free LLR Reordering
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Solution Overview
Problem
Traditional Low Density Parity Check (LDPC) codes are not widely adopted due to their complex encoding and decoding processes, which require large memory storage and additional logic circuitry, making them inefficient in terms of memory usage and power consumption.
Innovation Solution
A memory-efficient LDPC decoder is implemented by eliminating memory buffers associated with log-likelihood-ratio (LLR) data bits reordering, de-reordering, and demapping procedures, combining these operations to reduce memory storage and logic circuitry requirements, thereby minimizing die-size and power consumption in integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional LDPC decoding procedures (reordering, de-reordering, and demapping) are implemented with separate memory buffers, then decoding accuracy is maintained, but memory storage requirements and power consumption increase
Solution Approach 1:
The patent combines multiple decoding operations (reordering, de-reordering, and demapping) into a single integrated process that eliminates the need for separate memory buffers between these operations. By merging these functions into one computational pass, the patent reduces memory storage requirements while preserving decoding accuracy through careful design of the combined operation logic.
Solution Approach 2:
The patent extracts and eliminates unnecessary memory buffer components from the traditional LDPC decoding architecture. By removing the intermediate memory buffers that were previously required between reordering, de-reordering, and demapping operations, the patent reduces overall memory storage requirements while maintaining functional correctness through direct data flow between operations.
2Ease of operation
If traditional LDPC decoding procedures are implemented with separate memory buffers and logic circuitry, then decoding functionality is complete, but die-size and power consumption increase
Solution Approach 1:
The patent merges multiple decoding stages into a single integrated operational flow, reducing the total number of logic circuitry components and memory access operations. This consolidation decreases power consumption by eliminating redundant computational steps and reducing the overall complexity of the decoding logic while preserving complete decoding functionality.
Solution Approach 2:
The patent implements a continuous decoding process where data flows directly through reordering, de-reordering, and demapping operations without interruption or intermediate storage. This continuous action eliminates the need for repeated memory access cycles and logic circuitry activation, thereby reducing power consumption while maintaining full decoding capability.
3Reliability
If LDPC codes use large blocks to be effective, then error correction performance improves, but data memory storage space requirements increase
Solution Approach 1:
The patent combines multiple decoding operations into a single pass that processes large LDPC code blocks efficiently without requiring proportional increases in memory storage. By integrating reordering, de-reordering, and demapping into one operational sequence, the patent enables effective processing of large code blocks while minimizing memory space requirements through optimized data flow and computation.
Data Source
AI summary
A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.