LDPC LLR Memory Reuse to Cut Iteration Latency
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Solution Overview
Problem
Current LDPC code error-correcting systems are slowed by the need to read and write Log Likelihood Ratio (LLR) parameters from separate memory locations using high-speed buses and transmission lines, which increases latency and reduces the efficiency of the error-correcting process.
Innovation Solution
An integrated circuit with a single memory for storing both current and previous iterations of LLR parameters, allowing for reduced transmission connections and complexity, where the computational unit can overwrite and reuse these parameters efficiently, thereby reducing latency and increasing processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memory locations are used for storing current and previous iterations of LLR parameters, then data transmission can be performed, but transmission latency increases and processing speed decreases
Solution Approach 1:
The patent combines separate memory locations for current and previous LLR parameters into a single integrated memory structure. This merging eliminates the need for high-speed buses and transmission lines between separate memory locations, thereby reducing transmission latency while maintaining the ability to perform error correction operations.
2Speed
If high-speed buses and transmission lines are used to read and write LLR parameters, then data can be transmitted between memory locations, but the computational unit must wait for data transmission which reduces processing efficiency
Solution Approach 1:
By merging the memory locations into a single integrated memory, the patent eliminates the bottleneck of data transmission over buses and transmission lines. The computational unit can access both current and previous LLR parameters directly from the same memory location without waiting for inter-memory transmission, thus improving overall processing speed.
3Ease of operation
If separate memory locations are used for LLR parameters, then data can be stored and accessed, but the integrated circuit design becomes more complex and manufacturing costs increase
Solution Approach 1:
The patent simplifies the integrated circuit design by merging separate memory locations into a single memory structure. This reduces the number of memory components, buses, and transmission lines required, thereby lowering design complexity and manufacturing costs while maintaining full functionality for storing and accessing LLR parameters.
Data Source
AI summary
In one or more embodiments, a method, computer-readable media, and/or computational unit acts or is capable of receiving, from a single, integrated memory, current and previous iterations of Log Likelihood Ratio (“LLR”) parameters for a current iteration of a Low-Density Parity-Check code (“LDPC code”) error-correcting process. These may then perform an LDPC code error-correcting algorithm using the current and previous iterations of LLR parameters. Following this, these embodiment(s) may overwrite the previous iteration of LLR parameters with a now-current iteration of LLR parameters and treat the current iteration of LLR parameters as a now-previous iteration of LLR parameters. Both of these iterations of LLR parameters for the now-current iteration may then be received following overwrite of the previous iteration of LLR parameters with the now-current iteration of LLR parameters. With these now-current and now-previous iterations of LLR parameters these embodiment(s) may perform the LDPC code error-correcting algorithm.