LDPC Check Matrix and Interleaving for Burst-Error Tolerant Transmission

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Solution Overview

Problem

In data transmission using LDPC codes, ensuring favorable communication quality is challenging due to issues such as burst errors and erasures, which degrade decoding performance and increase power consumption.

Innovation Solution

The implementation of transmission and reception apparatuses and methods that utilize LDPC codes with a dual diagonal structure parity matrix and parity interleaving, along with bit and group-wise interleaving, to improve error rates and tolerate burst errors, thereby maintaining performance in AWGN channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LDPC codes are used for data transmission, then error correction capability is provided, but burst errors and erasures degrade communication quality

Engineering Contradiction:
Improvecommunication qualityVSAvoidburst errors and erasures
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies segmentation by dividing the code structure into information bits and parity bits with a dual diagonal parity matrix. This segmentation allows the parity bits to specifically address and correct burst errors and erasures, improving reliability without requiring complete code restructuring.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses a composite approach by combining LDPC coding with specific interleaving techniques (row interleaving and column interleaving). This composite structure creates a robust system that can handle both random errors and burst errors, effectively resolving the contradiction between maintaining error correction capability and resisting burst errors.

Inventive Principle:
Principle #40Composite materials

2Reliability

If code length is increased to improve error correction performance, then performance approaches Shannon limit, but system complexity increases

Engineering Contradiction:
Improveerror correction performanceVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the large code into manageable units through the dual diagonal parity matrix structure, where parity bits are systematically organized. This segmentation allows efficient decoding algorithms to process long codes without requiring exponential complexity, maintaining performance near the Shannon limit while controlling system complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the structural parameters of the parity check matrix to a dual diagonal form, which enables more efficient decoding algorithms. This parameter change maintains the error correction performance of long codes while reducing the computational complexity of the decoding process through the specialized matrix structure.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If interleaving techniques are applied to tolerate burst errors, then error rate improves, but processing time increases

Engineering Contradiction:
Improveerror rateVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the interleaving process into row interleaving and column interleaving stages, each handling specific aspects of error distribution. This segmented approach distributes burst errors more effectively across codewords while using optimized algorithms to minimize the time required for each interleaving stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary interleaving actions before decoding, organizing the code structure in advance to anticipate and mitigate burst error patterns. This preliminary structuring reduces the computational burden during actual decoding, thereby reducing processing time while maintaining improved error rate performance.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3544192B1Transmission scheme using LDPC codes of length 69120 and rate 13/16 and 14/16
Publication Date: 2021.07.28 SONY GROUP CORP
  • EP3544192B1 patent drawingFigure 1~2
  • EP3544192B1 patent drawingFigure 3
  • EP3544192B1 patent drawingFigure 4

AI summary

The present technique relates to a transmission apparatus, a transmission method, a reception apparatus, and a reception method that can ensure favorable communication quality in data transmission using an LDPC code. LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a code rate r of 13/16 or 14/16. The LDPC code includes information bits and parity bits, and the check matrix includes an information matrix corresponding to the information bits and a parity matrix corresponding to the parity bits. The information matrix is represented by a check matrix initial value table. The check matrix initial value table is a table indicating positions of elements of 1 in the information matrix on the basis of 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using the LDPC code.