LDPC Parity Check Matrix Layout for Burst Error Resistance
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Solution Overview
Problem
Existing data transmission systems using LDPC codes face challenges in maintaining favorable communication quality due to errors and erasures, particularly in burst error environments, which affect the decoding performance and power consumption.
Innovation Solution
The implementation of a transmission and reception system that performs LDPC coding using a parity check matrix with specific coding rates and interleaving techniques, such as parity interleaving and group-wise interleaving, to enhance error resistance and decoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC coding is performed using conventional parity check matrices, then decoding performance is maintained under standard conditions, but communication quality deteriorates in burst error environments
Solution Approach 1:
The parity check matrix is segmented into multiple sub-matrices with specific structures. The information matrix portion is divided into blocks that can be independently configured, allowing optimization for burst error resistance while maintaining overall decoding performance. This segmentation enables different parts of the matrix to handle different error patterns effectively.
Solution Approach 2:
Different regions of the parity check matrix are assigned different properties. The information matrix portion uses specific initial value tables configured for burst error resistance, while the parity matrix portion maintains structures optimized for decoding efficiency. This local differentiation allows simultaneous optimization for both error types.
2Adaptability or versatility
If LDPC coding with fixed parity check matrices is used, then implementation is simple, but adaptability to different error conditions is poor
Solution Approach 1:
The parity check matrix parameters, specifically the initial value tables, are changed based on the error conditions detected in the received signal. The system can switch between different initial value table configurations to adapt to burst errors or random errors. This parameter variability provides adaptability while maintaining a relatively simple fixed-matrix implementation approach for each configuration.
3Use of energy by moving object
If conventional LDPC decoding is performed, then decoding speed is maintained, but power consumption increases under high error conditions
Solution Approach 1:
The parity check matrix is pre-configured with specific structures and initial value tables that are optimized for burst error resistance before decoding begins. This preliminary configuration allows the decoding process to proceed more efficiently under high error conditions without requiring extensive iterative adjustments, thereby reducing power consumption while maintaining decoding effectiveness.
Data Source
AI summary
A transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed using a parity check matrix with the code length N of 17280 bits and the coding rate r of 13/16 or 14/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns.