LDPC Check Matrix and Interleaving for Burst-Error Tolerance
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Solution Overview
Problem
In data transmission using LDPC codes, ensuring favorable communication quality is challenging due to issues such as burst errors and erasures, which degrade decoding performance and increase power consumption.
Innovation Solution
The implementation of a transmission and reception system that employs LDPC codes with a dual diagonal structure parity matrix, combined with bit and parity interleaving, to improve error tolerance and decoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC codes are used for data transmission, then error correction capability is provided, but burst errors and erasures degrade decoding performance and increase power consumption
Solution Approach 1:
The code is divided into information bits and parity bits with distinct structural roles. The parity matrix is segmented into dual diagonal structures that specifically target burst error patterns, allowing the decoder to process different error types more efficiently and reduce overall power consumption while maintaining reliability.
Solution Approach 2:
The patent changes the structural parameters of the parity matrix to a dual diagonal form, which fundamentally alters how errors are distributed and detected. This parameter change enables the system to handle burst errors and erasures more effectively, improving decoding performance while the efficient structure reduces computational power consumption.
2Reliability
If LDPC codes are used for data transmission, then error correction capability is achieved, but burst errors and erasures occur that degrade communication quality
Solution Approach 1:
The dual diagonal parity matrix structure provides local quality optimization by concentrating error detection and correction capabilities in specific structural positions. This local structural enhancement specifically addresses burst error patterns without requiring changes to the entire code structure, thereby improving resistance to burst errors and erasures while maintaining overall error correction capability.
Solution Approach 2:
The parity bits are pre-calculated using the dual diagonal parity matrix structure before transmission. This preliminary action embeds error detection and correction information in advance, enabling the receiver to quickly identify and correct burst errors and erasures without requiring complex real-time processing, thus improving reliability against these harmful factors.
3Reliability
If bit and parity interleaving are implemented, then tolerance for burst errors and erasures is enhanced, but device complexity increases
Solution Approach 1:
The dual diagonal parity matrix introduces an asymmetric structure that naturally facilitates interleaving operations. This asymmetric design simplifies the interleaving process compared to symmetric structures, as the dual diagonal form provides clear patterns for bit and parity separation, thereby enhancing tolerance to burst errors and erasures while minimizing the increase in device complexity.
Data Source
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AI summary
The present technique relates to a transmission apparatus, a transmission method, a reception apparatus, and a reception method that can ensure favorable communication quality in data transmission using an LDPC code. LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a code rate r of 11/16 or 12/16. The LDPC code includes information bits and parity bits, and the check matrix includes an information matrix corresponding to the information bits and a parity matrix corresponding to the parity bits. The information matrix is represented by a check matrix initial value table. The check matrix initial value table is a table indicating positions of elements of 1 in the information matrix on the basis of 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using the LDPC code.