LDPC Parity Check Matrix Generation for Variable Code Block Sizes

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Solution Overview

Problem

Current quasi-cyclic-low-density parity-check (QC-LDPC) coding in 5G New Radio (NR) systems lacks optimization in code block size determination and parity check matrix generation, affecting performance and flexibility in wireless communication systems.

Innovation Solution

A method and apparatus that determine a code block size (CBS) and compare it with thresholds to calculate a Kb number, then use this number to determine a Kp number based on the code rate, generating a parity check matrix composed of circular permutation matrices for improved LDPC encoder or decoder operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If QC-LDPC coding is used in 5G NR systems with fixed code block size determination, then implementation is simpler, but performance and flexibility are reduced

Engineering Contradiction:
Improvecode block size flexibilityVSAvoidparity check matrix generation complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic code block size determination by comparing CBS with thresholds to calculate Kb number, which then determines Kp number based on code rate. This dynamic adaptation allows the system to optimize performance for different code block sizes and code rates while maintaining structured matrix generation through the relationship M = Kp × Kb.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes key parameters (Kb number and Kp number) based on code block size and code rate to optimize LDPC coding performance. By adjusting these parameters dynamically, the system achieves adaptability to different communication conditions while maintaining a systematic approach to parity check matrix generation.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If code block size is increased to improve throughput, then data transmission efficiency improves, but error correction capability may be compromised

Engineering Contradiction:
Improvedata transmission throughputVSAvoiderror correction capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent optimizes the balance between throughput and error correction by dynamically adjusting Kb and Kp parameters based on code block size and code rate. This parameter optimization ensures that larger code blocks maintain adequate error correction capability while achieving higher data transmission efficiency.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies different matrix construction strategies to different portions of the parity check matrix (information portion vs. overall structure), allowing optimized error correction for specific regions while maintaining overall system throughput efficiency.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3602795B1Generation of parity check matrices from a base graph in dependence on code block size and code rate
Publication Date: 2024.04.10 MEDIATEK INC
  • EP3602795B1 patent drawingFigure 1
  • EP3602795B1 patent drawingFigure 2A~2D
  • EP3602795B1 patent drawingFigure 3

AI summary

An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.