LDPC Parity Check Matrix Layout to Reduce Cycles and Complexity

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Solution Overview

Problem

The complexity and memory requirements of encoding and decoding using low density parity check (LDPC) codes are high due to the large size of the parity check matrix, which also leads to potential performance degradation from 4- or 6-cycles in the matrix.

Innovation Solution

The method involves configuring the parity check matrix H as [Hd|Hp], where Hd has sub-matrices with predetermined regularity in row or column weights, and Hp is a dual diagonal matrix, to reduce storage and computational complexity while minimizing 4- or 6-cycles, thereby enhancing decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the parity check matrix H is made very large to improve decoding performance, then performance approaches channel capacity limit, but memory storage space and computational complexity increase significantly

Engineering Contradiction:

Improvedecoding performanceVSAvoidcomputational complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The parity check matrix H is divided into multiple sub-matrices (first sub-matrix and second sub-matrix), allowing the decoding process to be performed in stages on smaller matrix segments rather than requiring simultaneous processing of the entire large matrix, thus reducing memory storage and computational complexity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first sub-matrix is configured in advance to prevent 4-cycles, and the second sub-matrix is configured to prevent 6-cycles, so that cycle prevention is performed preliminarily during matrix construction rather than requiring complex real-time detection during decoding operations

Inventive Principle:

Principle #10Preliminary action

2Reliability

If more weights are added to the parity check matrix H to improve performance, then more variables are added to parity check equations, but 4-cycle or 6-cycle may be generated causing performance degradation

Engineering Contradiction:

Improveencoding and decoding performanceVSAvoid4-cycle or 6-cycle generation

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The parity check matrix is segmented into two sub-matrices with distinct cycle-prevention responsibilities: the first sub-matrix focuses on preventing 4-cycles while the second sub-matrix focuses on preventing 6-cycles, allowing weight addition to be distributed and controlled to avoid harmful cycles

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the parity check matrix (different sub-matrices) are assigned different local properties: the first sub-matrix has properties optimized for 4-cycle prevention while the second sub-matrix has properties optimized for 6-cycle prevention, allowing each region to contribute differently to overall performance without generating harmful cycles

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS7814403B2Method of encoding and decoding using low density parity check code

Publication Date: 2010.10.12 LG ELECTRONICS INC

AI summary

A method of encoding and decoding using an LDPC code is disclosed, by which a memory for storing a parity check matrix necessary for the encoding or decoding using the LDPC code and calculation amount and complexity necessary for the encoding or decoding can be reduced. The present invention includes a step of encoding an input data using a parity check matrix H having a configuration of H=[Hd|Hp] (Hd is (n−k)×k dimensional, Hp is (n−k)×(n−k) dimensional, k is a bit number of the input data, and n is a bit number of a codeword), wherein if the Hd comprises a plurality of sub-matrices, each of the sub-matrices has predetermined regularity in a row or column weight.