LDPC Parity-Check Matrix Layout for Lower Decoding Complexity
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Solution Overview
Problem
Current LDPC code technologies face challenges in designing parity-check matrices that optimize performance for high-speed digital communication systems, particularly in overcoming noise, fading, and inter-symbol interference, while maintaining low encoding and decoding complexity.
Innovation Solution
The development of an LDPC encoding and decoding apparatus and method using parity-check matrices with specific structures, including information word and parity sub-matrices, defined by tables representing positions of value one, to improve code rate efficiency and error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC parity-check matrices are used, then encoding and decoding can be performed, but performance is limited due to suboptimal distribution of ones and high complexity
Solution Approach 1:
The parity-check matrix is divided into sub-matrices (information word sub-matrix and parity sub-matrix) with specific structures. Each sub-matrix has controlled distributions of ones, allowing independent optimization of different code rates while maintaining overall performance. This segmentation enables systematic design that reduces complexity through modular processing.
Solution Approach 2:
Different regions of the parity-check matrix are designed with different properties. The information word sub-matrix has a specific distribution pattern of ones optimized for certain code rates, while the parity sub-matrix has a complementary pattern. This local optimization allows the system to achieve better error correction performance without uniformly increasing complexity across the entire matrix.
2Reliability
If the distribution of ones in the parity-check matrix is optimized for better performance, then error correction capability improves, but encoding and decoding complexity increases
Solution Approach 1:
The invention optimizes specific parameters of the parity-check matrix including the distribution pattern of ones, the dimensions of sub-matrices, and the code rate configurations. By carefully selecting these parameters (such as the number of ones in specific positions and the structure of column blocks), the system achieves improved performance while controlling complexity through mathematical relationships rather than brute-force optimization.
3Productivity
If high code rate efficiency is achieved through optimized parity-check matrix structures, then data throughput improves, but the design complexity of the encoding apparatus increases
Solution Approach 1:
The encoding apparatus is designed to handle multiple code rates using a unified parity-check matrix structure. The same apparatus can operate at different code rates (such as 1/3, 2/3, 3/4, etc.) by utilizing different sub-matrices or different configurations of the same matrix structure. This multi-functionality achieves high code rate efficiency across various operating conditions without requiring separate specialized designs for each code rate.
Data Source
AI summary
An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.