LDPC Parity Check Matrix Layout for Encoding Through Decoding

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Solution Overview

Problem

Existing error correction methods for high-density data storage and transmission, such as Reed-Solomon and LDPC codes, require separate hardware for encoding and decoding, limiting their application in systems that perform iterative decoding like turbo codes, and struggle with efficiently generating parity check matrices for error correction in high-error environments.

Innovation Solution

A method for generating an M × N parity check matrix with a specific block structure, where the sub-matrix H_p has linearly independent row vectors organized into subsets, allowing for encoding through decoding using soft-iterative decoding, and minimizing the number of weight one columns to reduce encoding time and error correction complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate hardware is used for encoding and decoding, then encoding and decoding functions are fully implemented, but hardware complexity and system cost increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidhardware requirements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the encoding and decoding functions into a single LDPC decoder unit. The encoder is designed to perform both encoding and decoding operations using the same hardware resources, eliminating the need for separate encoding and decoding hardware. This is achieved by configuring the LDPC decoder to operate in encoding mode when receiving message vectors and in decoding mode when receiving codeword vectors with potential errors.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The LDPC decoder is designed as a universal device that can perform multiple functions: encoding, decoding, and error correction. By using the same hardware unit for both encoding and decoding operations, the system achieves multi-functionality without requiring separate dedicated hardware for each function, thereby reducing overall hardware complexity while maintaining full error correction capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If iterative decoding is used, then error correction performance is improved, but encoding cannot be performed with a single decoder

Engineering Contradiction:
Improveerror correction performanceVSAvoidencoding capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic functionality where the LDPC decoder can switch between encoding and decoding modes based on the input data characteristics. The encoder dynamically configures the same hardware unit to perform encoding operations by treating the message vector as input and generating the codeword vector, while maintaining the ability to perform iterative decoding operations when error correction is needed. This dynamic adaptability allows a single decoder to handle both encoding and decoding tasks.

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If high-density data storage is used, then storage capacity increases, but error occurrence rate increases

Engineering Contradiction:
Improvedata storage capacityVSAvoiderror rate
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent employs LDPC codes with specific parameter configurations (parity check matrix structure, code rate, block length) that are optimized for high-density storage environments. The encoder generates codewords with built-in redundancy based on these parameters, enabling the system to maintain high storage capacity while providing robust error correction capability to counteract the increased error rates inherent in high-density storage media.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP1798861B1LDPC encoding through decoding algorithm
Publication Date: 2008.11.05 SAMSUNG ELECTRONICS CO LTD
  • EP1798861B1 patent drawingFigure 1~2
  • EP1798861B1 patent drawingFigure 3A~3B
  • EP1798861B1 patent drawingFigure 4A~4B

AI summary

A parity check matrix making it possible to encode LDPLs through decoding, a method of generating a parity check matrix, an encoding method and an error correction apparatus including defining an M x N parity check matrix H = [Hm|Hp], and generating an M X M matrix as a sub-matrix Hp wherein all row vectors are linearly independent, a set A of all of the row vectors is a union set of non-empty subsets A1, A2, ..., Ak (1 ≤ k ≤ M) that do not include intersection sets with each other, A1 is a set of weight one row vectors, and Ai (2 ≤ i ≤ k) is a set of row vectors capable of deriving a weight one row vector by a linear combination with row vectors in a union set of the subsets A1, ..., Ai-1 among the row vectors not included in the union set.