LDPC Parity-Check Matrix Layout for Lower-Complexity Decoding
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Solution Overview
Problem
Current LDPC code technologies face challenges in designing parity-check matrices that optimize performance for high-speed digital communication systems, particularly in overcoming noise, fading, and inter-symbol interference, while maintaining efficient encoding and decoding processes.
Innovation Solution
The development of an LDPC encoding and decoding apparatus and method using parity-check matrices with specific structures, including information word and parity sub-matrices, defined by tables representing positions of value one, to improve code rate performance and error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes are decoded by applying sum-product algorithm based iterative decoding to the LDPC codes on a tanner graph, then the performance of the LDPC codes approaches the Shannon's channel capacity, but the complexity which could hardly be implemented at the technology level increases
Solution Approach 1:
The parity check matrix is divided into multiple sub-matrices (first through fourth sub-matrices), each handling specific portions of the encoding/decoding process. This segmentation allows the complex decoding operation to be broken down into manageable sub-operations that can be implemented more efficiently in hardware while maintaining the overall error correction performance.
Solution Approach 2:
The patent employs specific degree distributions for the parity check matrix columns (with degrees 2, 3, and 4) and uses optimized lifting values (e.g., L=120 for 64800-bit codewords) to improve convergence properties of the iterative decoder. These parameter optimizations enable the sum-product algorithm to achieve near-Shannon performance with reduced iteration counts, thereby lowering hardware complexity.
2Reliability
If the parity-check matrix is designed with specific structures including information word and parity sub-matrices, then the code rate performance and error correction capabilities are improved, but the design complexity increases
Solution Approach 1:
The parity check matrix H is segmented into four distinct sub-matrices (H1, H2, H3, H4) with specific structures. The information word sub-matrix and parity sub-matrix are further divided, allowing systematic construction where each sub-matrix has predefined patterns. This structured segmentation simplifies the design process by providing reusable templates while achieving optimized error correction performance.
Solution Approach 2:
The patent specifies precise parameters for the parity check matrix construction including column degrees (2, 3, 4), lifting values (L=60, 120, 180 depending on code rate), and specific non-zero element positions in each sub-matrix. These parameter specifications provide a systematic design methodology that reduces design complexity while optimizing performance for different code rates (1/3, 2/3, 3/4, 5/6).
Data Source
AI summary
An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.