LDPC Parity-Check Matrix Layout for Faster Encoding and Decoding
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Solution Overview
Problem
Existing LDPC codes face challenges in achieving high performance due to complex parity-check matrix designs, which affect encoding and decoding efficiency in high-speed digital communication systems.
Innovation Solution
The proposed solution involves designing a parity-check matrix with a specific structure, including an information word sub-matrix and a parity sub-matrix, defined by tables representing positions of value one in every 360-th column, to improve encoding and decoding performance for LDPC codes with code rates of 6/15, 8/15, 10/15, and 12/15.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complex parity-check matrix design is used for LDPC codes, then error correction performance is improved, but encoding and decoding efficiency deteriorates
Solution Approach 1:
The parity-check matrix is divided into multiple sub-matrices, where each sub-matrix corresponds to a specific code rate (6/15, 8/15, 10/15, 12/15). This segmentation allows the system to select an appropriate sub-matrix based on the required code rate, improving encoding and decoding efficiency while maintaining error correction performance through optimized matrix structures for each segment.
2Productivity
If a specific structured parity-check matrix is designed for multiple code rates, then encoding and decoding efficiency is improved, but the complexity of matrix design increases
Solution Approach 1:
The patent designs a universal parity-check matrix structure that can serve multiple code rates (6/15, 8/15, 10/15, 12/15) through different sub-matrices. This multi-functional design allows a single set of matrices to handle various coding scenarios, improving efficiency across different applications while managing design complexity through a systematic approach to matrix construction.
Data Source
AI summary
An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.