LDPC Parity-Check Matrix Layout for Faster Error Correction
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Solution Overview
Problem
Current LDPC code technologies face challenges in designing parity-check matrices that optimize performance and encoding/decoding complexity, particularly in achieving high reliability and throughput in high-speed digital communication systems, due to complexities in noise, fading, and inter-symbol interference.
Innovation Solution
The development of an LDPC encoding and decoding apparatus using a parity-check matrix with an information word sub-matrix and a parity sub-matrix, structured into column blocks and row blocks, defined by specific table representations to improve code rate performance, specifically for 6/15, 8/15, 10/15, and 12/15 code rates, enhancing the LDPC codeword generation and decoding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a parity-check matrix is designed to optimize error correction performance, then reliability is improved, but device complexity increases due to the complex structure requirements
Solution Approach 1:
The parity-check matrix is segmented into multiple column blocks, where each column block contains column groups with specific structures. This segmentation allows the matrix to achieve complex error correction capabilities while maintaining manageable structural organization through repeated patterns within each block.
Solution Approach 2:
Different column blocks are designed with different numbers of column groups (e.g., first column block has 36 column groups, second has 72 column groups), creating local variations in density and structure. This local quality differentiation optimizes error correction performance for different code rates while maintaining overall matrix manageability.
2Productivity
If the parity-check matrix uses more column groups to improve code rate performance, then productivity is improved, but device complexity increases
Solution Approach 1:
The parity-check matrix structure is designed to support multiple code rates (6/15, 8/15, 10/15, 12/15) using a universal framework of column blocks and column groups. By adjusting the number of column groups within this universal structure, the system achieves different code rates without requiring completely different matrix designs, thus improving productivity while controlling complexity.
3Reliability
If iterative decoding is applied to achieve Shannon channel capacity, then reliability is improved, but loss of time increases due to multiple iterations
Solution Approach 1:
The parity-check matrix is pre-designed with optimal column block structures and column group configurations that are tailored for iterative decoding performance. This preliminary structuring of the matrix ensures that the iterative decoding process converges faster and requires fewer iterations to achieve Shannon channel capacity, thus reducing the time loss associated with multiple decoding iterations.
Data Source
AI summary
An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.