LDPC Matrix Construction to Reduce Incident Cycles and Error Floor
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Solution Overview
Problem
Existing error correction codes, such as low-density parity check (LDPC) codes, suffer from an increased error floor due to the presence of incident cycles in the matrices used for code construction, which can lead to unexpected increases in bit error rates even in low-noise channels.
Innovation Solution
The method involves generating multiple matrices based on random numbers and additive candidate/test matrices, evaluating their weights indicative of extensibility, and selecting matrices that minimize incident cycles of a predetermined length to construct error correction codes in an in-order manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction codes are constructed using random matrices, then the construction process is simple and fast, but the error floor increases due to incident cycles causing unexpected increases in bit error rates
Solution Approach 1:
The patent applies preliminary action by evaluating and removing incident cycles of predetermined length during the matrix construction phase, before the error correction code is actually used for data transmission. This proactive approach prevents the formation of harmful cycle structures that would otherwise cause error floor issues during actual operation.
Solution Approach 2:
The patent extracts and removes incident cycles of predetermined length from the constructed matrices through a dedicated evaluation and removal process. By identifying and taking out these specific cycle structures, the method eliminates the source of error floor problems while preserving the overall random matrix structure that provides good error correction performance.
2Productivity
If matrices with incident cycles are used for error correction code construction, then the code construction is faster and simpler, but the bit error rate increases unexpectedly even in low-noise channels
Solution Approach 1:
The patent implements feedback by evaluating the constructed matrices for incident cycles and using this evaluation information to modify the matrix construction process. The feedback loop identifies matrices with problematic cycle structures and triggers re-construction or modification, ensuring that only matrices meeting the cycle-free criteria are used for final code construction.
Solution Approach 2:
The patent changes the parameters of the matrix construction process by introducing constraints on incident cycles of predetermined length. Rather than using purely random matrices, the method adjusts the construction parameters to avoid specific cycle structures, thereby changing the statistical properties of the matrices to achieve lower bit error rates while maintaining construction efficiency.
Data Source
AI summary
A non-transitory computer-readable medium and related method, including processing circuitry, which performs in-order error correction code construction. The processing circuitry receives a first plurality of matrices. The processing circuitry is to generate a second plurality of matrices based on at least one additive candidate matrix and each respective matrix of the first plurality of matrices. The processing circuitry then generates a third plurality of matrices based on at least one additive test matrix and each respective matrix of the second plurality of matrices. Each respective weight indicative of respective extensibility for each matrix of the second plurality of matrices is determined based on the third plurality of matrices. At least one matrix from the second plurality of matrices is then selected by processing circuitry based on the determined weights. The processing circuitry then generates an error correction code based on one of the at least one selected matrix.