LDPC Parity Check Matrix Structure for Lower BER Error Floors
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Solution Overview
Problem
Traditional LDPC codes suffer from high bit error rate (BER) error floors, which limit their performance in ultra-high speed optical transport networks.
Innovation Solution
The use of a parity check matrix with high performance characteristics, combined with a post-processing method like adaptive quantization, to minimize error floors and reduce memory and interconnection complexity in the decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional LDPC codes are used to achieve high NECG, then large block size is required, but this results in high BER error floors
Solution Approach 1:
The patent modifies the parity check matrix parameters by incorporating both RCP (Regular Column Partition) and QC (Quasi-Cyclic) constraints. This changes the structural parameters of the LDPC code to eliminate short cycles while maintaining large block size, thereby reducing BER error floors without proportionally increasing decoder complexity
Solution Approach 2:
The patent creates a composite code structure by combining RCP constraints with QC constraints in the parity check matrix. This composite approach integrates the benefits of both constraint types: RCP provides regular structure for simplified decoding while QC enables efficient implementation, achieving low error floors with manageable complexity
2Reliability
If concatenated codes are used to reduce error floors, then overhead increases and spectral efficiency decreases
Solution Approach 1:
The patent segments the parity check matrix into sub-matrices with specific RCP and QC structures. This segmentation allows the code to achieve low error floors through improved cycle structure without requiring outer concatenation codes, thereby avoiding the overhead and spectral efficiency loss associated with concatenated approaches
3Reliability
If large block size LDPC codes are used to achieve high NECG, then decoder memory and interconnection complexity increase
Solution Approach 1:
The patent changes the structural parameters of the parity check matrix by imposing RCP and QC constraints. This creates a more regular structure that can be decoded with reduced memory requirements and simpler interconnections, achieving high NECG without proportionally increasing hardware complexity
Solution Approach 2:
The QC-LDPC structure provides multi-functionality by enabling both high performance (high NECG) and efficient implementation (reduced complexity) through its cyclic properties. The same matrix structure serves both error correction performance and hardware implementation efficiency
Data Source
AI summary
A decoder for a receiver in a communication system includes an interface configured to receive encoded input data via a communication channel. The encoded input data includes forward error correction (FEC) codewords. A processor is configured to decode the FEC codewords using low density parity check (LDPC) codes defined by a parity check matrix. The parity check matrix is defined by both regular column partition (RCP) constraints and quasi-cyclic (QC) constraints. An output circuit is configured to output a decoded codeword based on the FEC codewords decoded by the processor.