LDPC Parity-Check Matrix Layout for Faster 64800-Bit Decoding

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current LDPC code technologies face challenges in improving encoding and decoding performance due to the complexity of designing effective parity-check matrices, which affects the reliability and efficiency of high-speed digital communication systems.

Innovation Solution

The development of a transmitting and receiving apparatus/method that employs a specific structure for the parity-check matrix, including a dual diagonal structure in the parity sub-matrix and a method for permuting rows and columns to optimize the LDPC code performance, utilizing a factor graph representation and iterative decoding algorithms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a parity-check matrix with dual diagonal structure is used, then encoding and decoding performance is improved, but device complexity increases

Engineering Contradiction:
Improveencoding and decoding performanceVSAvoidparity-check matrix structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The parity-check matrix is segmented into an information sub-matrix and a parity sub-matrix with distinct structures. The information sub-matrix uses an identity matrix structure while the parity sub-matrix employs a dual diagonal structure, allowing each segment to be optimized independently for its specific function while maintaining overall system performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the parity-check matrix are assigned different structural properties. The information sub-matrix region uses a simple identity structure for ease of encoding, while the parity sub-matrix region uses a dual diagonal structure optimized for decoding performance, creating local structural quality variations that improve overall reliability.

Inventive Principle:
Principle #3Local quality

2Reliability

If row and column permutation is applied to optimize LDPC code performance, then reliability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
ImproveLDPC code performanceVSAvoidpermutation implementation precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The optimal row and column permutation sequences are predetermined and stored in lookup tables before actual encoding/decoding operations. This preliminary preparation allows the system to simply retrieve and apply pre-optimized permutation patterns without requiring complex real-time optimization, reducing implementation precision requirements during operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The permutation operation transforms the parity-check matrix by changing the position parameters of rows and columns according to predetermined sequences. This parameter transformation approach allows systematic optimization of code performance through controlled repositioning while maintaining the underlying matrix structure and relationships.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If iterative decoding algorithms are used, then decoding performance approaches Shannon's channel capacity, but processing time increases

Engineering Contradiction:
Improvedecoding performanceVSAvoiddecoding processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The iterative decoding algorithm continuously refines probability estimates through multiple passes, with each iteration building upon the previous results. The process maintains continuous useful action by systematically updating message passing between check nodes and variable nodes until convergence or maximum iterations are reached, ensuring optimal performance while controlling processing time through structured iteration.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentEP3008826B1Method and apparatus for encoding and decoding of a code word of an LDPC code of length 64800 and rate 6/15
Publication Date: 2022.05.11 SAMSUNG ELECTRONICS CO LTD
  • EP3008826B1 patent drawingFigure 1~2
  • EP3008826B1 patent drawingFigure 3~4
  • EP3008826B1 patent drawingFigure 5A~5B

AI summary

An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.