LDPC Parity-Check Matrix Layout for High-Rate Error Correction
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Solution Overview
Problem
Current LDPC codes used in standards like DVB-S.2, DVB-T.2, and DVB-C.2 face challenges in achieving good error-rate performance, especially when transmitting large amounts of data such as 4K images, where prioritizing efficiency increases error rates, and there is a demand for various code rates with high error resistance.
Innovation Solution
A data processing apparatus and method that encodes and decodes LDPC codes with specific code lengths and rates, utilizing a parity check matrix with an information matrix portion and a parity matrix portion, represented by an initial value table showing positions of elements in units of 360 columns, to achieve efficient and robust error correction across different code rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes with larger code lengths are used to achieve performance closer to the Shannon limit, then error-rate performance is improved, but code complexity and processing overhead increase
Solution Approach 1:
The parity check matrix H is divided into multiple sub-matrices (first sub-matrix, second sub-matrix, third sub-matrix, fourth sub-matrix) arranged in a structured layout. This segmentation allows the large code to be processed in manageable blocks while maintaining the overall error-correcting performance, thus reducing processing complexity without sacrificing reliability.
Solution Approach 2:
Different regions of the parity check matrix have different properties - the information matrix portion and parity matrix portion are structured differently with specific row and column weight distributions. This local differentiation optimizes both error correction capability and decoding efficiency for different parts of the code structure.
2Productivity
If code rate is increased to improve transmission efficiency, then productivity is improved, but error resistance deteriorates
Solution Approach 1:
The patent provides multiple parity check matrix designs with different code rates (e.g., 1/2, 2/3, 3/4, 5/6, 7/8) and different row/column weight configurations. This allows the system to select appropriate parameters based on the desired balance between transmission efficiency and error resistance, optimizing performance for different communication scenarios.
Data Source
AI summary
A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The apparatus and method may be applied to LDPC encoding and LDPC decoding.