Rate-Compatible LDPC Parity Check Matrix via Inter-Block Shifts

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Solution Overview

Problem

Current technologies face challenges in generating rate-compatible quasi-cyclic Low Density Parity Check (LDPC) codes efficiently to support Incremental Redundancy Hybrid Automatic Repeat Request (IR HARQ) in 5G wireless communications, requiring complex implementations and high hardware throughput.

Innovation Solution

A method is proposed to generate rate-compatible Parity Check Matrices (PCMs) using a single PCM with multiple components, where component matrices are generated through inter-block cyclic shifts and interleaving of existing PCM components, optimizing the design to avoid small cycles and maintain a good girth profile, thereby simplifying implementation complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If rate-compatible quasi-cyclic LDPC codes are generated using conventional methods, then multiple code rates can be supported, but implementation complexity increases and hardware throughput requirements become more demanding

Engineering Contradiction:
Improvesupport for multiple code ratesVSAvoidimplementation complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The parity check matrix is divided into multiple components, where the first component matrix is independently designed and the second component matrix is generated through cyclic shifting of the first. This segmentation allows systematic generation of rate-compatible codes while reducing overall design complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different code rates are achieved by changing the ratio of information bits to parity bits through selective use of different component matrices. The girth parameter is optimized by carefully designing the cyclic shift amounts to avoid small cycles in the Tanner graph, thereby improving decoding performance while maintaining implementation simplicity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If conventional PCM generation methods are used, then error correction capability is achieved, but the girth profile may contain small cycles that degrade performance

Engineering Contradiction:
Improveerror correction capabilityVSAvoidgirth profile quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The cyclic shift amount parameter is carefully selected to ensure that the resulting Tanner graph has a good girth profile without small cycles. By adjusting this parameter, the patent optimizes the girth profile quality while maintaining the error correction capability provided by the LDPC code structure.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The first component matrix is designed in advance with specific properties, and the cyclic shift amount is predetermined to avoid small cycles. This preliminary design ensures that the resulting parity check matrix has the desired girth profile before actual encoding/decoding operations are performed.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If a single PCM is used for multiple code rates, then hardware throughput can be improved, but the complexity of generating rate-compatible codes increases

Engineering Contradiction:
Improvehardware throughputVSAvoidcomplexity of generating rate-compatible codes
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The parity check matrix is segmented into component matrices that can be systematically generated through cyclic shifting. This segmentation enables a single hardware implementation to support multiple code rates by simply activating different component matrices, thereby improving hardware throughput while keeping the generation complexity manageable through the structured approach.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent designs a universal parity check matrix structure that can serve multiple code rates. By using cyclic shifting to generate different component matrices from a base matrix, a single hardware implementation can handle multiple code rates, achieving multi-functionality and improving throughput efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10784895B2Inter-block modifications to generate sub-matrix of rate compatible parity check matrix
Publication Date: 2020.09.22 NOKIA TECHNOLOGIES OY
  • US10784895B2 patent drawing
  • US10784895B2 patent drawing
  • US10784895B2 patent drawing

AI summary

A method includes accessing information, and at least one of encoding or decoding the information using a parity check matrix based on a coding rate. A portion of a data part in the parity check matrix has been generated based on part or all of another matrix. Apparatus, computer programs, and computer program products are also described. The apparatus may be a wireless mobile device or a wireless network access node. A communication system may include one or more of the wireless mobile devices and one or more of the access nodes, each using a version of the method.