LDPC Parity-Check Matrix Layout for Faster Iterative Decoding

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Solution Overview

Problem

Existing LDPC code constructions face challenges in encoding difficulty, irregularity leading to non-optimal parallel decoding, and suboptimal convergence of decoding algorithms, particularly in quasi-cyclic and IRA codes, which affect the efficiency and speed of data transmission in digital communication systems.

Innovation Solution

A semi-regular parity check matrix is constructed with systematic and parity sub-matrices optimized for decoding convergence and hardware constraints, using specific permutation coefficients and scheduling rules to minimize memory access conflicts and enhance decoding speed, allowing for efficient parallel or semi-parallel processing in the decoder device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If quasi-cyclic LDPC codes are used, then decoding complexity is reduced, but encoding becomes difficult

Engineering Contradiction:

Improvedecoding complexityVSAvoidencoding difficulty

Core Design Contradiction:

Device complexityVSEase of manufacture

Solution Approach 1:

The parity check matrix H is divided into two submatrices: H1 (systematic part with random construction) and H2 (check part with bi-diagonal structure). This segmentation allows H1 to provide good error correction performance while H2 enables simplified encoding operations through its structured form.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different parts of the parity check matrix are assigned different properties: H1 uses random construction for optimal error correction, while H2 uses a deterministic bi-diagonal structure for simplified encoding. This local differentiation resolves the contradiction between encoding simplicity and decoding performance.

Inventive Principle:

Principle #3Local quality

2Ease of manufacture

If irregular repeat-accumulate codes are used, then encoding is simplified, but parallel decoding becomes suboptimal due to irregularity

Engineering Contradiction:

Improveencoding simplicityVSAvoidparallel decoding efficiency

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The code structure is made partially regular by imposing structure on H2 (the check part) while maintaining randomness in H1 (the systematic part). This local regularization enables more efficient parallel decoding without completely sacrificing the flexibility needed for good error correction performance.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The construction parameters of the parity check matrix are optimized to balance regularity and irregularity. By controlling the density and structure of H2, the code achieves better parallel decoding efficiency while maintaining the encoding simplicity characteristic of IRA codes.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If regular quasi-cyclic parity-check matrix is used, then parallel decoding is improved, but encoding becomes difficult

Engineering Contradiction:

Improveparallel decoding efficiencyVSAvoidencoding difficulty

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The parity check matrix adopts a hybrid structure where H1 maintains irregular random properties for good error correction, while H2 implements a regular bi-diagonal structure for efficient parallel decoding. This localized application of regularity resolves the contradiction between decoding efficiency and encoding simplicity.

Inventive Principle:

Principle #3Local quality

4Speed

If decoding algorithm is optimized for convergence speed, then resource usage increases due to multiple simultaneous memory accesses

Engineering Contradiction:

Improvedecoding convergence speedVSAvoidmemory access resources

Core Design Contradiction:

SpeedVSQuantity of substance

Solution Approach 1:

The parity check matrix is pre-constructed with a specific bi-diagonal structure in H2 that anticipates and prevents memory access conflicts during parallel decoding. This preliminary structural design enables faster convergence without proportionally increasing memory resource requirements.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentEP2092651B1Encoding and decoding of a data signal according to a correcting code

Publication Date: 2020.03.25 3G LICENSING SA

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Figure 2b~2e
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AI summary

The invention relates to the encoding and decoding of a data signal according to a correcting code. According to the invention, a signal including data variables is encoded into an encoded signal including data variables and parity variables. The encoding and decoding operations are based on a parity check matrix (H) formed by a systematic matrix (Hc) and a parity matrix (Hp), the lines of said check matrix corresponding to parity equation coefficients (eq1 - eqM) and being distributed in same-size decoding windows. In order to increase iterative decoding convergence, the elements from at least one column of the systematic matrix which are associated with a decoding window are all "0" except one element which is "1". A data variable is only involved in one equation from the window and is not involved in the equation resolution for other windows as long as the resolution of the equations from the window has not yet finished.