LDPC Parity Matrix Layout for Burst-Error-Resistant Reception
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Solution Overview
Problem
Existing data transmission systems using LDPC codes face challenges in maintaining favorable communication quality due to burst errors and erasures, particularly in AWGN channels and multipath environments, which affect the accuracy of decoding and increase power consumption.
Innovation Solution
The implementation of a transmission system that includes a parity interleaver and a block interleaver to separate parity bits and distribute them across multiple check nodes, improving resistance to burst errors and maintaining performance in AWGN channels through the use of a transformed parity check matrix with a pseudo cyclic structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If parity bits are concentrated in a specific position in the LDPC code structure, then the encoding and decoding process is simpler, but the system becomes more vulnerable to burst errors and erasures
Solution Approach 1:
The parity bits are segmented and distributed to different positions within the LDPC code structure. Instead of concentrating all parity bits together, they are spread across multiple locations according to the transformed parity check matrix with pseudo cyclic structure, which reduces vulnerability to burst errors while maintaining manageable encoding complexity through systematic distribution patterns.
Solution Approach 2:
The patent introduces a new structural dimension to the parity check matrix by applying a transformed version with pseudo cyclic structure. This transformation redistributes parity bits across different dimensions of the code structure (rows and columns), creating a more robust arrangement that resists burst errors without significantly increasing encoding complexity.
2Reliability
If LDPC codes use longer code lengths to approach Shannon limit performance, then error correction capability improves, but the processing time and power consumption increase
Solution Approach 1:
The patent employs preliminary actions by pre-defining the transformed parity check matrix structure with pseudo cyclic properties and pre-determining the parity bit distribution patterns. This preparation allows the encoding and decoding processes to proceed more efficiently without requiring complex real-time calculations, thus reducing processing time while maintaining the error correction benefits of longer code lengths.
3Reliability
If LDPC codes use longer code lengths to approach Shannon limit performance, then error correction capability improves, but power consumption in the reception device increases
Solution Approach 1:
By pre-defining the transformed parity check matrix structure and parity bit distribution patterns, the system reduces the computational burden during reception and decoding. This preliminary structuring allows the reception device to process longer LDPC codes with lower power consumption, as the predetermined patterns enable more efficient decoding algorithms without sacrificing error correction capability.
4Reliability
If parity bits are distributed across multiple check nodes, then resistance to burst errors improves, but the structure of the parity check matrix becomes more complex
Solution Approach 1:
The patent applies parameter changes by transforming the parity check matrix into a version with pseudo cyclic structure. This transformation modifies the structural parameters of the matrix while maintaining its fundamental properties, enabling parity bits to be distributed across multiple check nodes for improved burst error resistance without creating unmanageable structural complexity.
Data Source
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AI summary
The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 17280 bits and the coding rate r of 11/16 or 12/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns. The present technology can be applied to, for example, data transmission using an LDPC code.