LDPC Parity-Check Matrix Layout for Long Codeword Encoding
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Solution Overview
Problem
Existing LDPC codes face challenges in efficiently encoding and decoding messages with longer codeword block lengths, particularly in wireless communications like WiFi, due to the need for improved error correction and hardware compatibility.
Innovation Solution
The use of parity-check matrices (PCMs) for LDPC codes with a 2×1944 bit codeword block length, employing diagonal or off-diagonal expansions to generate 2×2 subblocks, optimizing girth and minimizing short cycles for enhanced error correction, while allowing hardware reuse through pre-lifting techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes with longer codeword block lengths are used to improve error correction capabilities, then reliability is improved, but device complexity and encoding/decoding efficiency deteriorate
Solution Approach 1:
The parity-check matrix is divided into multiple sub-blocks, where each sub-block corresponds to a specific portion of the codeword. This segmentation allows the encoding and decoding processes to be broken down into smaller, more manageable operations that can be performed in parallel or sequentially with reduced complexity at each stage, while still achieving the required error correction for longer codeword block lengths
Solution Approach 2:
The patent transforms the traditional single-dimension parity-check matrix into a two-dimensional structure with row sub-blocks and column sub-blocks. This dimensional change enables more efficient representation and processing of the parity-check relationships, reducing the computational burden associated with longer codeword block lengths while maintaining or improving error correction capabilities
2Productivity
If traditional encoding methods are used for longer codewords, then compatibility with existing systems is maintained, but encoding efficiency and hardware resource utilization deteriorate
Solution Approach 1:
The parity-check matrix structure and encoding method are designed to be universal and adaptable to different codeword lengths and code rates. The same fundamental encoding apparatus can handle various configurations by adjusting the parity-check matrix parameters, eliminating the need for multiple specialized hardware units and improving resource utilization while maintaining high encoding efficiency
Solution Approach 2:
The patent employs parameter changes in the parity-check matrix, such as varying the number of row sub-blocks, column sub-blocks, and the dimensions of individual sub-blocks, to optimize encoding efficiency for different application requirements. These parameter adjustments allow the system to achieve high encoding efficiency without requiring complex hardware reconfiguration, thereby improving productivity while controlling device complexity
Data Source
AI summary
One example discloses a method for encoding a message, comprising: receiving a set of message-data-bits; generating a set of parity-bits based on the set of message-data-bits; wherein the parity-bits are generated by multiplying the set of message-data-bits with a generator matrix derived from a corresponding parity-check matrix (PCM) of an LDPC code; wherein the LDPC code has a total codeword block length of 2×1944 bits; and generating an encoded message that includes both the set of message-data-bits and the set of parity-bits.