LDPC Check Matrix Layout for Low-SNR Wireless Transmission
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Solution Overview
Problem
Existing information transmission systems using Low-Density Parity-Check (LDPC) codes face challenges in securing excellent communication quality, particularly in wireless communication schemes like LPWA, where interference and low signal-to-noise ratios can impact data reliability.
Innovation Solution
A transmitting and receiving apparatus and method employing LDPC coding with a check matrix of 736 bits and 1/4 code rate, utilizing a stepwise structured parity matrix and a check matrix initial value table to indicate positions of elements '1' in the information matrix, enabling repeated modulation and demodulation to improve signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC coding with conventional check matrices is used, then error correction capability is provided, but communication quality deteriorates under low signal-to-noise ratio conditions
Solution Approach 1:
The patent applies parameter changes by modifying the check matrix structure to have a stepwise parity matrix portion with specific properties. The information matrix portion is constructed using a check matrix initial value table with carefully selected parameters (columns of 8 elements each, specific element positions marked as '1'). This parameter optimization enables the LDPC code to achieve excellent communication quality with block error probability below 10^-5 at signal-to-noise ratios of 0.5 dB or less, directly resolving the contradiction between reliability and susceptibility to low signal-to-noise ratio conditions.
2Object-affected harmful factors
If repetition units with LDPC codes are used for modulation, then signal-to-noise ratio is enhanced, but transmission time increases
Solution Approach 1:
The patent employs partial action by using repetition units containing LDPC codes of specific lengths (736 bits, 1472 bits, 2944 bits, or 5888 bits) rather than repeating all possible code lengths. The check matrix is designed with an information matrix portion of 184 bits and parity matrix portion of 552 bits for the 736-bit code, creating an optimized balance between repetition for signal enhancement and transmission time. This partial repetition strategy achieves the desired signal-to-noise ratio improvement while minimizing transmission time loss.
3Reliability
If check matrix with stepwise parity matrix portion is used, then decoding performance is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the check matrix into distinct functional portions: an information matrix portion (184x184 elements) and a parity matrix portion (552x736 elements with stepwise structure). The information matrix is further segmented into columns of 8 elements each, with specific element positions (indicated by '1' in the check matrix initial value table) strategically placed to optimize decoding performance. This segmented structure improves decoding performance while managing device complexity through systematic organization.
Solution Approach 2:
The patent employs preliminary action by pre-defining the check matrix initial value table with specific element positions before actual encoding and decoding operations. The table specifies exactly which positions contain '1' elements in the information matrix portion, eliminating the need for complex real-time calculations during transmission. This preliminary structuring of the check matrix reduces device complexity while maintaining improved decoding performance through the optimized stepwise parity matrix structure.
Data Source
AI summary
LDPC coding is executed using a check matrix of an LDPC code whose code length is 736 bits and whose code rate is 1/4, and modulation is executed using a repetition unit that has an LDPC code obtained by the LDPC coding, repeatedly arranged therein. The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the parity matrix portion has a stepwise structure, the information matrix portion is indicated by a check matrix initial value table, and the check matrix initial value table is a predetermined table indicating positions of elements of “1” of the information matrix portion for each eight columns. This technique is applicable to, for example, information transmission using the LDPC code.