LDPC Parity-Check Matrix Expansion for Parallel MIMO Encoding

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Solution Overview

Problem

Existing MIMO (multiple-input multiple-output) OFDM systems, such as IEEE 802.11n, face challenges in implementing high-performance error correction due to the optional nature of LDPC codes, which are crucial for efficient error control in wireless communication systems.

Innovation Solution

A MIMO transmitter is designed with a forward error correction encoder that applies a parity check matrix derived from a base matrix, incorporating LDPC encoding to prevent sequences of adjacent noisy bits and ensuring efficient data transmission by using a scrambler, interleaver, QAM mapping, and inverse fast Fourier transform modules.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LDPC codes are implemented in MIMO OFDM systems, then error correction performance is improved, but device complexity increases

Engineering Contradiction:
Improveerror correction performanceVSAvoidencoder complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The LDPC encoder is divided into multiple parallel encoding units that process different portions of the input data simultaneously. Each encoding unit handles a segment of the codeword generation, allowing the overall encoding task to be distributed across multiple processing elements, thereby reducing the complexity burden on any single unit while maintaining high error correction performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from sequential encoding to parallel encoding by introducing a temporal or spatial dimension to the encoding process. Multiple encoding operations that would traditionally execute one after another are arranged to operate concurrently, effectively adding a parallel processing dimension that reduces overall encoding complexity and increases throughput.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If parallel encoding units are used, then encoding speed is improved, but synchronization difficulty increases

Engineering Contradiction:
Improveencoding speedVSAvoidsynchronization complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A synchronization mechanism is implemented that monitors the operational state of each parallel encoding unit and provides feedback control signals to adjust their timing and coordination. This feedback loop ensures that all encoding units remain synchronized during parallel operation, preventing data mismatches and ensuring correct codeword generation while maintaining high encoding speed.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

An intermediary control unit is introduced that acts as a mediator between the multiple parallel encoding units and the final output assembly process. This intermediary coordinates the output from each encoding unit, ensuring proper timing and synchronization before combining the results, thereby managing the synchronization complexity centrally rather than requiring complex point-to-point coordination between all units.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If code rate is increased, then data transmission efficiency is improved, but error correction capability deteriorates

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoiderror correction capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system implements dynamic parameter adjustment that modifies encoding characteristics based on channel conditions and required performance levels. By changing parameters such as the density of the parity check matrix or the allocation of redundancy bits, the system can optimize the balance between code rate and error correction capability, achieving higher data transmission efficiency when channel conditions permit while maintaining sufficient error correction when needed.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8762809B1LDPC codes and expansion method
Publication Date: 2014.06.24 MARVELL ASIA PTE LTD
  • US8762809B1 patent drawing
  • US8762809B1 patent drawing
  • US8762809B1 patent drawing

AI summary

An apparatus includes a circuit configured to at least one of (i) encode first data to produce encoded data or (ii) decode second data to produce decoded data. The circuit is configured to operate according to a predetermined matrix. Each element of the predetermined matrix labeled with a hyphen corresponds to a zero matrix. Each element of the predetermined matrix labeled with a number corresponds to a respective cyclic-permutation matrix.